C8051F817-GS Silicon Laboratories Inc, C8051F817-GS Datasheet - Page 235

• Manufacturer Part Number: C8051F817-GS
• Description: IC MCU 8BIT 8K FLASH 16SOIC
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F81xr

Specifications of C8051F817-GS

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Processor Series: C8051F8x
• Core: 8051
• Data Bus Width: 16 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F800DK
• Minimum Operating Temperature: - 55 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1792-5

29.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may be operated in 16-Bit PWM mode. 16-bit PWM mode is independent of the other (8-bit
through 15-bit) PWM modes. In this mode, the 16-bit capture/compare module defines the number of PCA
clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the out-
put on CEXn is asserted high; when the 16-bit counter overflows, CEXn is asserted low. 16-Bit PWM Mode
is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register.
The duty cycle of the PWM output signal can be varied by writing to an “Auto-Reload” Register, which is
dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0. This synchronous update feature allows software to asynchro-
nously write a new PWM high time, which will then take effect on the following PWM period.
For backwards-compatibility with the 16-bit PWM mode available on other devices, the PWM duty cycle
can also be changed without using the “Auto-Reload” register. To output a varying duty cycle without using
the “Auto-Reload” register, new value writes should be synchronized with PCA CCFn match interrupts.
Match interrupts should be enabled (ECCFn = 1 AND MATn = 1) to help synchronize the capture/compare
register writes. If the MATn bit is set to 1, the CCFn flag for the module will be set each time a 16-bit com-
parator match (rising edge) occurs. The CF flag in PCA0CN can be used to detect the overflow (falling
edge). The duty cycle for 16-Bit PWM Mode is given by Equation 29.4.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Using Equation 29.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
P C A 0C P Ln
W rite to
R eset
P C A 0C P H n
W rite to
0
E N B
E N B
1
W
M
P
1
6
n
1
C
O
M
E
n
P C A 0C P M n
C
A
P
P
n
0 0 x 0
C
A
P
N
n
M
A
T
n
O
G
T
n
Equation 29.4. 16-Bit PWM Duty Cycle
Figure 29.10. PCA 16-Bit PWM Mode
W
M
P
n
Duty Cycle
E
C
C
F
n
x
P C A T im ebase
A R S E L = 1
A R S E L = 0
R /W w hen
R /W w hen
E nable
=
16-bit C om parator
(C apture/C om pare )
P C A 0C P H :Ln
P C A 0C P H :Ln
Rev. 1.0

---------------------------------------------------- -
(A uto -R eload )
P C A 0H :L
65536 PCA0CPn
–
65536
O verflow
M atch
R
A
S
E
L
S
E
C
O
V
R
P C A 0P W M
x

C
O
V
F
S E T
C LR
C8051F80x-83x
Q
Q
E
A
R
1
6
C
L
S
E
L
2
x x x
C
S
E
L
L
1
C E X n
C
S
E
L
L
0
C rossbar
P ort I/O
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