C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 181

• Manufacturer Part Number: C8051F705-GM
• Description: IC 8051 MCU 15K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F705-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 15KB (15K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 32 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 1.9 V, 3.6 V
• Supply Voltage (min): 1.7 V, 1.8 V
• Width: 7 mm
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1612-5

28.1. Port I/O Modes of Operation
Port pins P0.0 - P6.5 use the Port I/O cell shown in Figure 28.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a
high impedance state with weak pull-ups enabled. Until the crossbar is enabled (XBARE = 1), both the
high and low port I/O drive circuits are explicitly disabled on all crossbar pins.
28.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, Capacitive Sense input, external oscillator input/output,
VREF output, or AGND connection should be configured for analog I/O (PnMDIN.n = 0). When a pin is
configured for analog I/O, its weak pullup, digital driver, and digital receiver are disabled. Port pins config-
ured for analog I/O will always read back a value of 0.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital I/O may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
28.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external event trigger functions, or as
GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output modes
(push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the out-
put logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only
drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high
low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption, and they may be globally disabled by
setting WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or
driven to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read
back the logic state of the Port pad, regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
To/From Analog
Peripheral
PxMDIN.x
(1 for digital)
(0 for analog)
Figure 28.2. Port I/O Cell Block Diagram
Rev. 1.0
VDD
GND
C8051F70x/71x
VDD
(WEAK)
PORT
PAD
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