C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 55

• Manufacturer Part Number: C8051F705-GM
• Description: IC 8051 MCU 15K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F705-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 15KB (15K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 32 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 1.9 V, 3.6 V
• Supply Voltage (min): 1.7 V, 1.8 V
• Width: 7 mm
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1612-5

10. 10-Bit ADC (ADC0)
ADC0 on the C8051F700/2/4/6/8 and C8051F710/2/4/6 is a 500 ksps, 10-bit successive-approximation-
register (SAR) ADC with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a pro-
grammable window detector. The ADC is fully configurable under software control via Special Function
Registers. The ADC may be configured to measure various different signals using the analog multiplexer
described in Section “10.5. ADC0 Analog Multiplexer” on page 65. The voltage reference for the ADC is
selected as described in Section “11. Temperature Sensor” on page 67. The ADC0 subsystem is enabled
only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is
in low power shutdown when this bit is logic 0.
AMUX0
From
X1 or
X0.5
AMP0GN0
Figure 10.1. ADC0 Functional Block Diagram
AIN
ADC0CF
ADC
10-Bit
VDD
SAR
Rev. 1.0
ADC0GTH ADC0GTL
ADC0LTH
ADC0CN
ADC0LTL
Conversion
Start
C8051F70x/71x
000
001
010
011
100
101
32
AD0WINT
Compare
Window
CNVSTR Input
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
Timer 3 Overflow
Logic
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