C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 200

• Manufacturer Part Number: C8051F705-GM
• Description: IC 8051 MCU 15K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F705-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 15KB (15K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 32 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 1.9 V, 3.6 V
• Supply Voltage (min): 1.7 V, 1.8 V
• Width: 7 mm
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1612-5

C8051F70x/71x
SFR Definition 28.17. P2: Port 2
SFR Address = 0xA0; SFR Page = All Pages; Bit Addressable
SFR Definition 28.18. P2MDIN: Port 2 Input Mode
SFR Address = 0xF3; SFR Page = F
200
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
P2MDIN[7:0]
P2[7:0]
Name
Name
7
1
7
1
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
6
1
6
1
Description
5
1
5
1
Rev. 1.0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
1
4
1
P2MDIN[7:0]
P2[7:0]
R/W
R/W
Function
Write
3
1
3
1
2
1
2
1
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
1
1
1
1
Read
0
1
0
1