PIC16F684-E/P Microchip Technology, PIC16F684-E/P Datasheet - Page 62

• Manufacturer Part Number: PIC16F684-E/P
• Description: IC PIC MCU FLASH 2KX14 14DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F684-E/P

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 14-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163029 - BOARD PICDEM FOR MECHATRONICSACICE0207 - MPLABICE 14P 300 MIL ADAPTER
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F684
A persistent mismatch condition will preclude clearing
the CxIF interrupt flag. Reading CMCON0 will end the
mismatch condition and allow the CxIF bit to be
cleared.
FIGURE 8-6:
FIGURE 8-7:
DS41202F-page 60
Q1
Q3
CxIN+
CxOUT
Set CMIF (level)
CMIF
Q1
Q3
CxIN+
CxOUT
Set CMIF (level)
CMIF
Note 1: If a change in the CM1CON0 register
cleared by CMCON0 read
2: When either comparator is first enabled,
(CxOUT) should occur when a read oper-
ation is being executed (start of the Q2
cycle), then the CxIF Interrupt Flag bit of
the PIR1 register may not get set.
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable.
Allow about 1 μs for bias settling then clear
the mismatch condition and interrupt flags
before enabling comparator interrupts.
T
T
RT
RT
COMPARATOR
INTERRUPT TIMING W/O
CMCON0 READ
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
reset by software
reset by software
8.6
The comparator, if enabled before entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is shown separately in
Section 15.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comparator. The comparator is turned off
by selecting mode CM<2:0> = 000 or CM<2:0> = 111
of the CMCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CxIE bit of the PIE1 register
and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the interrupt service routine.
8.7
A device Reset forces the CMCON0 and CMCON1
registers to their Reset states. This forces the Compar-
ator module to be in the Comparator Reset mode
(CM<2:0> = 000). Thus, all comparator inputs are
analog inputs with the comparator disabled to consume
the smallest current possible.
Operation During Sleep
Effects of a Reset
© 2007 Microchip Technology Inc.