ATTINY48-AUR Atmel, ATTINY48-AUR Datasheet - Page 111

• Manufacturer Part Number: ATTINY48-AUR
• Description: MCU AVR 4KB FLASH 12MHZ 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 12-5.
8008G–AVR–04/11
Mode
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
WGM
13
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Waveform Generation Mode Bit Description
WGM
12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 12-4
correct or the phase and frequency correct, PWM mode.
Table 12-4.
Note:
• Bits 3:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 1:0 – WGM1[1:0]: Waveform Generation Mode
Combined with the WGM1[3:2] bits found in the TCCR1B Register, these bits control the count-
ing sequence of the counter, the source for maximum (TOP) counter value, and what type of
waveform generation to be used, see
COM1A1
COM1B1
WGM
11
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set.
shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the phase
“Phase Correct PWM Mode” on page 103.
WGM
10
COM1A0
COM1B0
Compare Output Mode, Phase Correct and Phase & Frequency Correct PWM
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Timer/Counter
Mode of Operation
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase & Frequency Correct
PWM, Phase & Frequency Correct
PWM, Phase Correct
PWM, Phase Correct
CTC
(Reserved)
Fast PWM
Fast PWM
Description
Normal port operation, OC1A/OC1B disconnected.
WGM1[3:0] = 8, 9, 10 or 11: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings, normal
port operation, OC1A/OC1B disconnected.
Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B
on Compare Match when downcounting.
Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B
on Compare Match when downcounting.
Table
12-5.
for more details.
TOP
0xFFFF
0x00FF
0x01FF
0x03FF
OCR1A
0x00FF
0x01FF
0x03FF
ICR1
OCR1A
ICR1
OCR1A
ICR1
–
ICR1
OCR1A
Update of
OCR1
Immediate
TOP
TOP
TOP
Immediate
TOP
TOP
TOP
BOTTOM
BOTTOM
TOP
TOP
Immediate
–
TOP
TOP
ATtiny48/88
x
at
BOTTOM
TOV1 Flag
Set on
MAX
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
MAX
–
TOP
TOP
See
111
(1)