ATTINY261A-MN Atmel, ATTINY261A-MN Datasheet - Page 37

• Manufacturer Part Number: ATTINY261A-MN
• Description: IC MCU AVR 2K FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261A-MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 128 B, 256 B, 512 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 105 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.4.5
7.4.6
7.5
7.5.1
8197B–AVR–01/10
Register Description
Watchdog Timer
Port Pins
MCUCR – MCU Control Register
If the Watchdog Timer is not needed in the application, this module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important thing is then to ensure that no pins drive resistive loads. In sleep modes where
both the I/O clock (clk
will be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0, DIDR1).
Refer to
able Register 1” on page 159
The MCU Control Register contains control bits for power management.
• Bit 7 – BODS: BOD Sleep
In order to disable BOD during sleep the BODS bit must be written to logic one. This is controlled
by a timed sequence and the enable bit, BODSE. First, both BODS and BODSE must be set to
one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to
zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be exe-
cuted while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit
is automatically cleared after three clock cycles.
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
• Bits 4, 3 – SM1:0: Sleep Mode Select Bits 2:0
Bit
0x35 (0x55)
Read/Write
Initial Value
“DIDR0 – Digital Input Disable Register 0” on page 159
“Watchdog Timer” on page 42
7
BODS
R/W
0
CC
/2 on an input pin can cause significant current even in active mode. Digital
I/O
6
PUD
R/W
0
) and the ADC clock (clk
CC
for details.
“Digital Input Enable and Sleep Modes” on page 57
/2, the input buffer will use excessive power.
5
SE
R/W
0
4
SM1
R/W
0
for details on how to configure the Watchdog Timer.
ADC
3
SM0
R/W
0
) are stopped, the input buffers of the device
2
BODSE
R/W
0
or
“DIDR1 – Digital Input Dis-
1
ISC01
R/W
0
0
ISC00
R/W
0
for details on
MCUCR
37