ATTINY48-MMHR Atmel, ATTINY48-MMHR Datasheet - Page 186

• Manufacturer Part Number: ATTINY48-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 28QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY48-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.1.3
19.1.4
19.2
19.2.1
186
Register Description
ATtiny48/88
Preventing Flash Corruption
Programming Time for Flash when Using SPM
SPMCSR – Store Program Memory Control and Status Register
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
The calibrated oscillator is used to time Flash accesses.
ming time for Flash accesses from the CPU.
Table 19-1.
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bit 7 – Res: Reserved Bit
This bit is reserved and will always read zero.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in ATtiny48/88.
Bit
0x37 (0x57)
Read/Write
Initial Value
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-down sleep mode during periods of low V
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low V
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
SPM Programming Time
R
7
–
0
Symbol
RWWSB
CC
R
6
0
, the Flash program can be corrupted because the supply voltage is
R
5
–
0
CTPB
R/W
4
0
Min Programming Time
RFLB
R/W
3
0
3.7 ms
Table 19-1
PGWRT
R/W
2
0
CC
PGERS
shows the typical program-
reset protection circuit
R/W
1
0
Max Programming Time
CC
SELFPRGEN
. This will pre-
R/W
4.5 ms
0
0
8008G–AVR–04/11
SPMCSR