ATTINY24A-SSN Atmel, ATTINY24A-SSN Datasheet - Page 4

• Manufacturer Part Number: ATTINY24A-SSN
• Description: IC MCU AVR 2KB FLASH 20MHZ 14SOI
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY24A-SSN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Overview
4
ATtiny24A/44A/84A
ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Figure 2-1.
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
GND
VCC
PROGRAMMING
INSTRUCTION
Block Diagram
PROGRAM
PROGRAM
REGISTER
INSTRUCTION
COUNTER
CONTROL
DECODER
FLASH
LINES
LOGIC
DATA REGISTER
PORT A
PORT A DRIVERS
ISP INTERFACE
PA[7:0]
REGISTERS
POINTER
REGISTER
PURPOSE
GENERAL
STATUS
STACK
SRAM
ALU
X
Y
Z
REG.PORT A
DATA DIR.
8-BIT DATABUS
ADC
MCU CONTROL
MCU STATUS
OSCILLATOR
WATCHDOG
INTERRUPT
REGISTER
REGISTER
INTERNAL
COUNTER0
COUNTER1
EEPROM
TIMER/
TIMER/
DATA REGISTER
TIMER
UNIT
PORT B
PORT B DRIVERS
PB[3:0]
OSCILLATORS
CALIBRATED
OSCILLATOR
TIMING AND
REG.PORT B
INTERNAL
CONTROL
DATA DIR.
8183CS–AVR–03/11