ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 312

• Manufacturer Part Number: ATMEGA88-20MUR
• Description: MCU AVR 8K FLASH 20MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88-20MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: MLF EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

312
ATmega48/88/168
Figure 28-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
Table 28-8.
Symbol
V
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
XLWL
XLPH
PLXH
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
WLRH
WLRH_CE
PP
XTAL1
DATA
BS1
XA0
XA1
OE
1. The timing requirements shown in
reading operation.
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
Timing Requirements
Parallel Programming Characteristics, V
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
t
XLOL
t
OLDV
(1)
(1)
(LOW BYTE)
DATA (Low Byte)
READ DATA
Figure 28-7
t
BVDV
(2)
(that is, t
CC
= 5V ±10%
11.5
Min
200
150
150
150
150
(HIGH BYTE)
3.7
7.5
READ DATA
67
67
67
67
67
67
67
0
0
0
DATA (High Byte)
DVXH
, t
XHXL
t
Typ
OHDZ
, and t
LOAD ADDRESS
XLDX
(LOW BYTE)
ADDR1 (Low Byte)
Max
12.5
250
4.5
1
9
) also apply to
2545S–AVR–07/10
Units
ms
μA
ns
μs
V