ATMEGA8535L-8AUR Atmel, ATMEGA8535L-8AUR Datasheet - Page 143

• Manufacturer Part Number: ATMEGA8535L-8AUR
• Description: MCU AVR 8K FLASH 8MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Status Register – SPSR
SPI Data Register – SPDR
2502K–AVR–10/06
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low
when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing
the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register
with WCOL set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega8535 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode (see Table 59). This means that the minimum SCK period will
be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-
teed to work at f
The SPI interface on the ATmega8535 is also used for program memory and EEPROM
downloading or uploading. See page 251 for Serial Programming and verification.
The SPI Data Register is a read/write register used for data transfer between the Regis-
ter File and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register receive buffer to be read.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SPIF
MSB
R/W
R
X
7
0
osc
7
/4 or lower.
WCOL
R/W
R
X
6
0
6
R/W
R
X
5
–
0
5
R/W
R
4
–
0
4
X
R/W
3
–
R
0
3
X
R/W
R
X
2
–
0
2
ATmega8535(L)
R/W
R
X
1
–
0
1
SPI2X
R/W
LSB
R/W
0
0
0
X
Undefined
SPSR
SPDR
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