ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 119

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.11.7.4
9132D–AUTO–12/10
Phase Correct PWM Mode
The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope opera-
tion. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.
In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the com-
pare match between TCNT0 and OCR0A while upcounting, and set on the compare match
while downcounting. In inverting Output Compare mode, the operation is inverted. The
dual-slope operation has lower maximum operation frequency than single slope operation.
However, due to the symmetric feature of the dual-slope PWM modes, these modes are pre-
ferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the coun-
ter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for
one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
ure
dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent compare matches between
OCR0A and TCNT0.
Figure 4-36. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
interrupt flag can be used to generate an interrupt each time the counter reaches the BOT-
TOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0A1:0 to three (See
125). The actual OC0A value will only be visible on the port pin if the data direction for the port
pin is set as output.
TCNTn
OCnxi
OCnxi
Period
4-36. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the
1
2
Atmel ATA6616/ATA6617
3
4
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
Table 4-32 on page
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Fig-
119