ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 77

• Manufacturer Part Number: ATA6616-P3QW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3QW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9132D–AUTO–12/10
Figure 4-22. Watchdog Timer
The WDT gives an interrupt or a system reset when the counter reaches a given time-out
value. In normal operation mode, it is required that the system uses the WDR - Watchdog
Timer Reset - instruction to restart the counter before the time-out value is reached. If the sys-
tem doesn't restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be
used to wake the device from sleep-modes, and also as a general system timer. One example
is to limit the maximum time allowed for certain operations, giving an interrupt when the opera-
tion has run longer than expected. In System Reset mode, the WDT gives a reset when the
timer expires. This is typically used to prevent system hang-up in case of runaway code. The
third mode, Interrupt and System Reset mode, combines the other two modes by first giving
an interrupt and then switch to System Reset mode. This mode will for instance allow a safe
shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to
System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter-
rupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,
alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP)
MONITORING
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit.
as desired, but with the WDCE bit cleared. This must be done in one operation.
CLOCK
WATCHDOG
OSCILLATOR
WDIE
WDIF
WDE
~128 KHz
RESET
WDP0
WDP1
WDP2
WDP3
Atmel ATA6616/ATA6617
PRESCALER
WATCHDOG
MCU
RESET
INTERRUPT
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