ATMEGA32U2-MUR Atmel, ATMEGA32U2-MUR Datasheet - Page 150

• Manufacturer Part Number: ATMEGA32U2-MUR
• Description: MCU AVR 32K FLASH 16MHZ 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U2-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

18.3.1
7799D–AVR–11/10
Internal Clock Generation – The Baud Rate Generator
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 18-2
Figure 18-2. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
osc
rxclk
txclk
xcko
xcki
f
), is loaded with the UBRRn value each time the counter has counted down to zero or when
OSC
DDR_XCK
XCK
Pin
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master operation.
XTAL pin frequency (System Clock).
shows a block diagram of the clock generation logic.
xcko
xcki
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/2
Figure
osc
ATmega8U2/16U2/32U2
/(UBRRn+1)). The Transmitter divides the
/4
18-2.
/2
DDR_XCK
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
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