ATMEGA32U2-MUR Atmel, ATMEGA32U2-MUR Datasheet - Page 51

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ATMEGA32U2-MUR

Manufacturer Part Number
ATMEGA32U2-MUR
Description
MCU AVR 32K FLASH 16MHZ 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA32U2-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
10.3
10.3.1
10.4
10.4.1
10.4.2
7799D–AVR–11/10
Internal Voltage Reference
Watchdog Timer
Voltage Reference Enable Signals and Start-up Time
Features
Overview
that remains enabled. This allows the device to stay attached to the bus during and after the
reset, while enhancing firmware reliability.
Figure 10-7. USB Reset During Operation
ATmega8U2/16U2/32U2 features an internal bandgap reference. This reference is used for
Brown-out Detection, and it can be used as an input to the Analog Comparator.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the
reference to start up before the output from the Analog Comparator is used. To reduce power
consumption in Power-down mode, the user can avoid the three conditions above to ensure that
the reference is turned off before entering Power-down mode.
ATmega8U2/16U2/32U2 has an Enhanced Watchdog Timer (WDT). The WDT is a timer count-
ing cycles of a separate on-chip 128 kHz oscillator. The WDT gives a early warning interrupt
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
Clocked from separate On-chip Oscillator
3 Operating modes
Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
Early warning after one Time-Out period reached, programmable Reset (see operating modes)
after 2 Time-Out periods reached.
– Interrupt
– System Reset
– Interrupt and System ResetSelectable Time-out period from 16ms to 8s
ACBG bit in ACSR).
DM
DP
CC
USB Traffic
“System and Reset Characteristics” on page
ATmega8U2/16U2/32U2
End of Reset
USB Traffic
267. To save power, the
51

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