ATMEGA164PA-AU Atmel, ATMEGA164PA-AU Datasheet - Page 60
ATMEGA164PA-AU
Manufacturer Part Number
ATMEGA164PA-AU
Description
MCU AVR 16KB FLASH 20MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA164PA-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
2-Wire/SPI/USART
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Package
44TQFP
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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10.4.2
8272A–AVR–01/10
WDTCSR – Watchdog Timer Control Register
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-
tem Reset will be applied.
Table 10-1.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x60)
Read/Write
Initial Value
WDTON
1
1
1
1
0
Watchdog Timer Configuration
WDIF
R/W
WDE
7
0
0
0
1
1
x
WDIE
R/W
6
0
WDIE
0
1
0
1
x
WDP3
R/W
5
0
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
WDCE
R/W
4
0
WDE
R/W
X
3
WDP2
R/W
2
0
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
WDP1
R/W
1
0
WDP0
R/W
0
0
WDTCSR
60
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