PIC16LC62B-04/SS Microchip Technology, PIC16LC62B-04/SS Datasheet - Page 35

• Manufacturer Part Number: PIC16LC62B-04/SS
• Description: IC MCU OTP 2KX14 PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC62B-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

7.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• driven High
• driven Low
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). The inter-
rupt flag bit, CCP1IF, is set on all compare matches.
FIGURE 7-2:
TABLE 7-3
Address
0Bh,8Bh
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
Legend:
RC2/CCP1
Pin
1999 Microchip Technology Inc.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>), which starts an A/D
conversion
Output Enable
TRISC<2>
Compare Mode
x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Name
INTCON
PIR1
PIE1
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
Q
Special Event Trigger
COMPARE MODE
OPERATION BLOCK
DIAGRAM
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
R
S
CCP1CON<3:0>
Mode Select
Output
PORTC Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
Logic
Bit 7
GIE
—
—
—
—
(PIR1<2>)
Set flag bit CCP1IF
match
ADIE
Bit 6
PEIE
ADIF
—
—
CCPR1H CCPR1L
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
TMR1H
Comparator
Bit 5
T0IE
—
—
TMR1L
CCP1Y
Bit 4
INTE
Preliminary
—
—
CCP1M3
SSPIE
SSPIF
RBIE
Bit 3
7.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
7.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
7.2.3
When a generated software interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
7.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP1 resets the TMR1
register pair and starts an A/D conversion (if the A/D
module is enabled).
Note:
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP1IE TMR2IE
CCP1IF
Bit 2
T0IF
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
PIC16C62B/72A
TMR2IF
Bit 1
INTF
TMR1IF -0-- 0000 -0-- 0000
TMR1IE -0-- 0000 -0-- 0000
Bit 0
RBIF
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR,
BOR
DS35008B-page 35
Value on
all other
resets