PIC16F916-I/SP Microchip Technology, PIC16F916-I/SP Datasheet - Page 182

• Manufacturer Part Number: PIC16F916-I/SP
• Description: IC PIC MCU FLASH 8KX14 28SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F916-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SSP/I2C/AUSART/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F91X
15.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value.
RC5/T1CKI/CCP1/SEG10 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 15-4:
15.2.1
The user must configure the RC5/T1CKI/CCP1/SEG10
pin as an output by clearing the TRISC<2> bit.
15.2.2
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
DS41250B-page 180
CCP1/SEG10
RC5/T1CKI/
Note:
Special event trigger will:
pin
Output Enable
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
TRISC<2>
Compare Mode
When
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC5/T1CKI/CCP1/SEG10 compare
output latch to the default low level. This is
not the PORTC I/O data latch.
TIMER1 MODE SELECTION
Q
Special Event Trigger
R
S
CCP1CON<3:0>
Mode Select
Output
a
Logic
COMPARE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<2>)
Set Flag bit CCP1IF
match
Match
CCPR1H CCPR1L
TMR1H
occurs,
Comparator
TMR1L
Preliminary
the
15.2.3
When Generate Software Interrupt mode is chosen, the
RC5/T1CKI/CCP1/SEG10 pin is not affected. The
CCPIF bit is set, causing a CCP interrupt (if enabled).
15.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
15.3
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
RC5/T1CKI/CCP1/SEG10 pin is multiplexed with the
PORTC data latch, the TRISC<2> bit must be cleared
to make the RC5/T1CKI/CCP1/SEG10 pin an output.
Figure 15-5 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.3.3
“Setup for PWM Operation”.
Note:
Note:
PWM Mode (PWM)
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
 2004 Microchip Technology Inc.