PIC16F76T-I/SO Microchip Technology, PIC16F76T-I/SO Datasheet - Page 293

• Manufacturer Part Number: PIC16F76T-I/SO
• Description: IC MCU FLASH 8KX14 A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F76T-I/SO

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.3.7
17.3.8
INTCON
PIR
PIE
SSPBUF
SSPCON1
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The position of this bit is device dependent.
1997 Microchip Technology Inc.
Name
2: These bits may also be named GPIE and GPIF.
Shaded cells are not used by the SSP in SPI mode.
Sleep Operation
Effects of a Reset
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
Bit 7
SMP
GIE
In master mode all module clocks are halted, and the transmission/reception will remain in that
state until the device wakes from sleep. After the device returns to normal mode, the module will
continue to transmit/receive data.
In slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This
allows the device to be placed in sleep mode, and data to be shifted into the SPI transmit/receive
shift register. When all 8-bits have been received, the MSSP interrupt flag bit will be set and if
enabled will wake the device from sleep.
A reset disables the MSSP module and terminates the current transfer.
Table 17-1: Registers Associated with SPI Operation
PEIE
Bit 6
CKE
Bit 5
T0IE
D/A
INTE RBIE
Bit 4
P
SSPIF
SSPIE
Preliminary
Bit 3
S
(1)
(1)
(2)
Bit 2
T0IF
R/W
INTF
Bit 1
Section 17. MSSP
UA
RBIF
Bit 0
BF
(2)
0000 0000
xxxx xxxx
0000 0000
0000 0000
Value on
POR,
BOR
0
0
DS31017A-page 17-17
other resets
Value on all
0000 0000
uuuu uuuu
0000 0000
0000 0000
0
0
17