PIC16F76T-I/SO Microchip Technology, PIC16F76T-I/SO Datasheet - Page 329

• Manufacturer Part Number: PIC16F76T-I/SO
• Description: IC MCU FLASH 8KX14 A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F76T-I/SO

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 22
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.4.18.2 Bus Collision During a Repeated Start Condition
1997 Microchip Technology Inc.
SDA
SCL
RSEN
BCLIF
S
SSPIF
During a Repeated Start condition, a bus collision occurs if:
a)
b)
When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with
SSPADD<6:0>, and counts down to zero. The SCL pin is then de-asserted, and when sampled
high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e. another master,
Figure
is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus
collision occurs, because no two masters can assert SDA at exactly the same time.
If, however, SCL goes from high to low before the BRG times out and SDA has not already been
asserted, then a bus collision occurs. In this case, another master is attempting to transmit a data
’1’ during the Repeated Start condition,
If at the end of the BRG time out both SCL and SDA are still high, the SDA pin is driven low, the
BRG is reloaded, and begins counting. At the end of the count, regardless of the status of the
SCL pin, the SCL pin is driven low and the Repeated Start condition is complete.
Figure 17-38: Bus Collision During a Repeated Start Condition (Case 1)
A low level is sampled on SDA when SCL goes from low level to high level.
SCL goes low before SDA is asserted low, indicating that another master is attempting to
transmit a data ’1’.
17-38, is attempting to transmit a data ’0’). If, however, SDA is sampled high then the BRG
Preliminary
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
Figure
17-39.
Section 17. MSSP
Cleared in software
'0'
'0'
DS31017A-page 17-53
17