ATMEGA32U2-AU Atmel, ATMEGA32U2-AU Datasheet - Page 166

• Manufacturer Part Number: ATMEGA32U2-AU
• Description: IC MCU 8BIT 32KB FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U2-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 22
• Eeprom Memory Size: 1KB
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

18.10.2
7799D–AVR–11/10
Transmission Flow Control
stop sending characters. RTS usage and so associated flow control is enabled using RTSEN bit
in UCSRnD.
Figure 18-8. shows a reception example.
Figure 18-8. Reception Flow Control Waveform Example
Figure 18-9. RTS behavior
RTS will rise at 2/3 of the last received stop bit if the receive fifo is full.
To ensure reliable transmissions, even after a RTS rise, an extra-data can still be received and
stored in the Receive Shift Register.
The transmission flow can be controlled by hardware using the CTS pin controlled by the exter-
nal receiver. The aim of the flow control is to stop transmission when the receiver is full of data
(CTS = 1). CTS usage and so associated flow control is enabled using CTSEN bit in UCSRnD.
The CTS pin is sampled at each CPU write and at the middle of the last stop bit that is
curently being sent.
Figure 18-10. CTS behavior
Read from CPU
Write from CPU
RXD
RTS
TXD
CTS
sample
Start
Start
Index
FIFO
RXD
RTS
Byte0
Byte0
Stop
Stop
0
sample
C1 C2
ATmega8U2/16U2/32U2
1
Start
Start
2
CPU Read
1
Byte1
Byte1
C3
0
Stop
Stop
1
sample
1 additional byte may be sent
if the transmitter misses the RTS trig
Start
Start
Byte2
Byte2
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