ATMEGA32U2-AU Atmel, ATMEGA32U2-AU Datasheet - Page 85

• Manufacturer Part Number: ATMEGA32U2-AU
• Description: IC MCU 8BIT 32KB FLASH 32TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32U2-AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AVR MEGA
• No. Of I/o's: 22
• Eeprom Memory Size: 1KB
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

13.2.2
7799D–AVR–11/10
EICRB – External Interrupt Control Register B
interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the
EIFR Register before the interrupt is re-enabled.
Table 13-1.
Note:
• Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7:4 Sense Control Bits
The External Interrupts [7:4] are activated by the external pins INT[7:4] if the SREG I-flag and
the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins
that activate the interrupts are defined in
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the comple-
tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low.
Table 13-2.
Note:
Bit
(0x6A)
Read/Write
Initial Value
ISCn1
ISCn1
0
0
1
1
0
0
1
1
1. n = 3, 2, 1or 0.
1. n = 7, 6, 5 or 4.
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
ISCn0
0
1
0
1
0
1
0
1
Interrupt Sense Control
Interrupt Sense Control
ISC71
R/W
7
0
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request
The falling edge between two samples of INTn generates an interrupt request.
The rising edge between two samples of INTn generates an interrupt request.
Description
The low level of INTn generates an interrupt request.
Any edge of INTn generates asynchronously an interrupt request.
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
ISC70
R/W
6
0
ISC61
R/W
5
0
(1)
(1)
Table
ISC60
R/W
4
0
13-2. The value on the INT[7:4] pins are sampled
ATmega8U2/16U2/32U2
ISC51
R/W
3
0
ISC50
R/W
2
0
ISC41
R/W
1
0
ISC40
R/W
0
0
EICRB
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