PIC24FJ128GA106-E/MR Microchip Technology, PIC24FJ128GA106-E/MR Datasheet - Page 187

• Manufacturer Part Number: PIC24FJ128GA106-E/MR
• Description: IC PIC MCU FLASH 128K 64-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA106-E/MR

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3
To compute the Baud Rate Generator reload value, use
Equation 16-1.
EQUATION 16-1:
TABLE 16-1:
TABLE 16-2:
 2009 Microchip Technology Inc.
Note 1:
Note 1:
Note 1: Based on F
Slave Address
Required System
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
2: These clock rate values are for guidance only.
2:
2:
3:
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
Setting Baud Rate When
Operating as a Bus Master
I2CxBRG
1 MHz
1 MHz
1 MHz
or
F
F
are disabled.
The actual clock rate can be affected by various
system level parameters. The actual clock rate
should be measured in its intended application.
SCL
SCL
Based on F
These clock rate values are for guidance only. The actual clock rate can be affected by various system
level parameters. The actual clock rate should be measured in its intended application.
The address bits listed here will never cause an address match, independent of address mask settings.
The address will be Acknowledged only if GCEN = 1.
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
=
--------------------------------------------------------------------- -
I2CxBRG
I
I
2
2
=
C™ CLOCK RATES
C™ RESERVED ADDRESSES
CY
R/W Bit


COMPUTING BAUD RATE
RELOAD VALUE
----------- -
F
CY
= F
F
SCL
0
1
x
x
x
x
x
x
CY
OSC
= F
+ +
–
F
/2, Doze mode and PLL
1
OSC
----------------------------- -
10 000 000
CY
General Call Address
Start Byte
Cbus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-Bit Slave Upper Byte

16 MHz
16 MHz
16 MHz
----------------------------- -
10 000 000
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2, Doze mode and PLL are disabled.
F
F
CY

CY

F
CY



(1,2)
–
(1,2)
1
PIC24FJ256GA110 FAMILY
(Decimal)
(2)
(1)
157
(3)
78
39
37
18
13
9
4
6
3
I2CxBRG Value
16.4
The I2CxMSK register (Register 16-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK
is set to ‘00010000’, the slave module will detect both
addresses: ‘0000000’ and ‘0010000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Note:
Description
(Hexadecimal)
Slave Address Masking
As a result of changes in the I
col, the addresses in Table 16-2 are
reserved and will not be Acknowledged in
Slave mode. This includes any address
mask settings that include any of these
addresses.
9D
4E
27
25
12
D
9
4
6
3
1.026 MHz
1.026 MHz
0.909 MHz
DS39905D-page 187
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
Actual
99 kHz
F
SCL
2
C™ proto-