AT89C5130A-RDRUM Atmel, AT89C5130A-RDRUM Datasheet - Page 112

MCU 8051 16K FLASH USB 64-VQFP

AT89C5130A-RDRUM

Manufacturer Part Number
AT89C5130A-RDRUM
Description
MCU 8051 16K FLASH USB 64-VQFP
Manufacturer
Atmel
Series
AT89C513xr
Datasheet

Specifications of AT89C5130A-RDRUM

Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89STK-05
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C5130A-RDRUM
Manufacturer:
Atmel
Quantity:
10 000
Table 20-6.
112
SSSTA
Status
Code
08h
10h
38h
40h
48h
50h
58h
Status of the Two-
wire Bus and Two-
wire Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
Arbitration lost in
SLA+R or NOT ACK
bit
SLA+R has been
transmitted; ACK has
been received
SLA+R has been
transmitted; NOT ACK
has been received
Data byte has been
received; ACK has
been returned
Data byte has been
received; NOT ACK
has been returned
AT89C5130A/31A-M
Status in Master Receiver Mode
To/From SSDAT
Write SLA+R
Write SLA+R
Write SLA+W
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
No SSDAT action
Read data byte
Read data byte
Read data byte
Read data byte
Read data byte
Application software response
SSSTA
X
X
X
0
1
0
0
1
0
1
0
0
1
0
1
SSSTO
To SSCON
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
SSI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SSAA
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
Next Action Taken by Two-wire Hardware
SLA+R will be transmitted.
SLA+R will be transmitted.
SLA+W will be transmitted.
Logic will switch to master transmitter mode.
Two-wire bus will be released and not addressed
slave mode will be entered.
A START condition will be transmitted when the bus
becomes free.
Data byte will be received and NOT ACK will be
returned.
Data byte will be received and ACK will be returned.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
Data byte will be received and NOT ACK will be
returned.
Data byte will be received and ACK will be returned.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
4337K–USB–04/08

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