AT89C5130A-M

Manufacturer Part NumberAT89C5130A-M
ManufacturerAtmel Corporation
AT89C5130A-M datasheets
 


Specifications of AT89C5130A-M

Flash (kbytes)16 KbytesMax. Operating Frequency48 MHz
Cpu8051-12CMax I/o Pins34
Usb Transceiver1Usb SpeedFull Speed
Usb InterfaceDeviceSpi1
Twi (i2c)1Uart1
Sram (kbytes)1.25Eeprom (bytes)1024
Self Program MemoryAPIOperating Voltage (vcc)2.7 to 5.5
Timers4IspUART/USB
WatchdogYes  
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Features
80C52X2 Core (6 Clocks per Instruction)
– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode
– Dual Data Pointer
– Full-duplex Enhanced UART (EUART)
– Three 16-bit Timer/Counters: T0, T1 and T2
– 256 Bytes of Scratchpad RAM
16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
3-KbyteFlash EEPROM for Bootloader
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
1-Kbyte EEPROM Data (
– Byte and Page (128 bytes) Erase and Write
– 100k Write Cycles
On-chip Expanded RAM (ERAM): 1024 Bytes
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers: 32-byte FIFO
– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
• Endpoint 1, 2, 3: 32-byte FIFO
• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)
• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode)
– Suspend/Resume Interrupts
– 48 MHz PLL for Full-speed Bus Operation
– Bus Disconnection on Microcontroller Request
5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed
Output, Compare/Capture, PWM and Watchdog Timer Capabilities
Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 100 ms
to 3s at 8 MHz
Keyboard Interrupt Interface on Port P1 (8 Bits)
TWI (Two Wire Interface) 400Kbit/s
SPI Interface (Master/Slave Mode)
34 I/O Pins
4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical
4-level Priority Interrupt System (11 sources)
Idle and Power-down Modes
0 to 24 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis
Industrial Temperature Range
Extended Range Power Supply: 2.7V to 5.5V (3.3V to 5.5V required for USB)
Packages: PLCC52, VQFP64, QFN32
8-bit Flash
Microcontroller
with Full Speed
USB Device
AT89C5130A-M
AT89C5131A-M

AT89C5130A-M Summary of contents

  • Page 1

    ... Idle and Power-down Modes • MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis • Industrial Temperature Range • Extended Range Power Supply: 2.7V to 5.5V (3.3V to 5.5V required for USB) • Packages: PLCC52, VQFP64, QFN32 8-bit Flash Microcontroller with Full Speed USB Device AT89C5130A-M AT89C5131A-M ...

  • Page 2

    ... RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator. In addition, AT89C5130A/31A-M has an on-chip expanded RAM of 1024 bytes (ERAM), a dual data pointer, a 16-bit up/down Timer (T2), a Programmable Counter Array (PCA pro- grammable LED current sources, a programmable hardware watchdog and a power-on reset ...

  • Page 3

    ... EUART 16/32Kx8Flash 4Kx8 RAM + 256x8 BRG C51 CORE Parallel I/O Ports & Ext. Bus Timer 0 INT Ctrl Timer 1 Port 0Port 1 Port 2 Port 3 (2) (2) (2) (2) AT89C5130A/31A-M (1) (1) (1) (1) (1) (1) (1) (1) (3) (3) ERAM 1Kx8 PCA SPI Timer2 TWI Key Watch Regu- USB Board Dog ...

  • Page 4

    ... Pinout Description 3.1 Pinout Figure 3-1. AT89C5130A/31A-M 4 AT89C5130A/31A-M 52-pin PLCC Pinout P4.1/SDA 8 9 P2.3/A11 P2.4/A12 10 P2.5/A13 11 12 XTAL2 13 XTAL1 PLCC52 14 P2.6/A14 P2.7/A15 15 VDD 16 AVDD 17 UCAP 18 AVSS 19 P3.0/RxD P0.1/AD1 44 P0.2/AD2 43 RST 42 P0.3/AD3 41 VSS 40 P0 ...

  • Page 5

    ... Figure 3-2. 4337K–USB–04/08 AT89C5130A/31A-M 64-pin VQFP Pinout P2.3/A11 3 P2.4/A12 4 P2.5/A13 5 XTAL2 6 XTAL1 7 P2.6/A14 8 P2.7/A15 VQFP64 9 VDD 10 AVDD 11 UCAP 12 AVSS P3.0/RxD AT89C5130A/31A ...

  • Page 6

    ... Figure 3-3. 3.2 Signals All the AT89C5130A/31A-M signals are detailed by functionality on Table 3-1 through Table 3- 12. Table 3-1. Table 3-2. AT89C5130A/31A-M 6 AT89C5130A/31A-M 32-pin QFN Pinout P4.1/SDA 1 XTAL2 2 XTAL1 3 VDD 4 UCAP 5 AVSS 6 P3.0/RxD 7 PLLF Note : The metal plate can be connected to Vss ...

  • Page 7

    ... When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer/Counter 1 External Clock Input T1 I When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count. I Timer/Counter 2 External Clock Input T2 O Timer/Counter 2 Clock Output T2EX I Timer/Counter 2 Reload/Capture/Direction Control Input AT89C5130A/31A-M Alternate Function P1.3 P1.4 P1.5 P1.6 P1.7 Alternate Function P3.0 P3.1 Alternate Function P3.2 P3 ...

  • Page 8

    ... Table 3-5. Table 3-6. Table 3-7. AT89C5130A/31A-M 8 LED Signal Description Signal Name Type Description Direct Drive LED Output These pins can be directly connected to the Cathode of standard LEDs LED[3:0] O without external current limiting resistors. The typical current of each output can be programmed by software mA. Several outputs can be connected together to get higher drive capabilities ...

  • Page 9

    ... Output of the on-chip inverting oscillator amplifier XTAL2 O To use the internal oscillator, a crystal/resonator circuit is connected to this pin external oscillator is used, leave XTAL2 unconnected. PLL Low Pass Filter input PLLF I Receive the RC network of the PLL low pass filter. AT89C5130A/31A-M Alternate Function AD[7: KIN[7:0] T2 T2EX ECI ...

  • Page 10

    ... Table 3-10. Table 3-11. Table 3-12. AT89C5130A/31A-M 10 USB Signal Description Signal Name Type Description USB Data + signal D+ I/O Set to high level under reset. USB Data - signal D- I/O Set to low level under reset. USB Reference Voltage VREF O Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function. ...

  • Page 11

    ... Low Power versions. USB pull-up Controlled Output VREF is used to control the USB D+ 1.5 kΩ pull up. VREF O The Vref output is in high impedance when the bit DETACH is set in the USBCON register. AT89C5130A/31A-M Figure 4-1 on page 12) Alternate Function - - - ...

  • Page 12

    ... The following figure represents the typical wiring schematic. Figure 4-1. VDD USB VBUS D+ D- GND VSS 2.2nF VSS AT89C5130A/31A-M 12 Typical Application VDD 100nF 4.7µF VSS VSS 1.5K VRef AT89C5130A/31A-M 27R D+ 27R D- UVSS UCAP 1µF +20% VSS PLLF 100R 10nF VSS VSS 100nF VSS XTAL1 22pF Q 22pF ...

  • Page 13

    ... VRef possible, isolate D+ and D- signals from other signals with ground wires USB PLL Components must be close to the microcontroller Isolate filter components with a ground wire AT89C5130A/31A-M Wires must be routed in Parallel and must be as short as possible USB Connector AVss PLLF 13 ...

  • Page 14

    ... Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller. The AT89C5130A/31A-M X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 5-1) that can be configured with off-chip components as a Pierce oscillator (see Figure 5-2). Value of capacitors and crystal characteristics are detailed in the section “ ...

  • Page 15

    ... PLL 5.3.1 PLL Description The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 5-3 shows the internal structure of the PLL. The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the ...

  • Page 16

    ... Figure 5-5. 5.3.3 Divider Values To generate a 48 MHz clock using the PLL, the divider values have to be configured following the oscillator frequency. The typical divider values are shown in Table 5-1. AT89C5130A/31A-M 16 PLL Filter Connection PLLF VSS PLL Programming Flow PLL ...

  • Page 17

    ... Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. System Clock Control bit Clear to select 12 clock periods per machine cycle (STD mode 2). OSC Set to select 6 clock periods per machine cycle (X2 mode, F AT89C5130A/31A-M R+1 N SIX2 ...

  • Page 18

    ... Reset Value = 0000 0000b Table 5-3. Reset Value = 0000 0000b Table 5-4. Reset Value = 0000 0000b Table 5-5. AT89C5130A/31A-M 18 CKCON1 (S:AFh) Clock Control Register Bit Bit Number Mnemonic Description Reserved 7-1 - The value read from this bit is always 0. Do not set this bit. ...

  • Page 19

    ... Reset Value = 0000 0000 4337K–USB–04/08 Bit Bit Number Mnemonic Description 7-4 R3:0 PLL R Divider Bits 3-0 N3:0 PLL N Divider Bits AT89C5130A/31A-M 19 ...

  • Page 20

    ... SFR Mapping The Special Function Registers (SFRs) of the AT89C5130A/31A-M fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...

  • Page 21

    ... SSCON SSCS 0000 0000 1111 1000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C AT89C5130A/31A-M 5/D 6/E 7/F CCAP3H CCAP4H XXXX XXXX XXXX XXXX CCAP3L CCAP4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 X000 0000 UEPRST ...

  • Page 22

    ... CCh Timer/Counter 2 Low byte Timer/Counter 0 and 1 TCON 88h control Timer/Counter 0 and 1 TMOD 89h Modes T2CON C8h Timer/Counter 2 control T2MOD C9h Timer/Counter 2 Mode AT89C5130A/31A-M 22 C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register Program Status PSW D0h Word Stack Pointer ...

  • Page 23

    ... BRR CCF4 CIDL WDTE ECOM0 CAPP0 CAPN0 ECOM1 CAPP1 CAPN1 ECOM2 CAPP2 CAPN2 ECOM3 CAPP3 CAPN3 ECOM4 CAPP4 CAPN4 AT89C5130A/31A TB8 RB8 TBCK RBCK SPD SRC CCF3 ...

  • Page 24

    ... A3h PLL Control PLLDIV A4h PLL Divider Table 6-10. Keyboard SFRs Mnemonic Add Name Keyboard Flag KBF 9Eh Register Keyboard Input Enable KBE 9Dh Register AT89C5130A/31A CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP3H7 CCAP3H6 ...

  • Page 25

    ... EEORINT EPEN - - - DIR RXOUTB1 STALLRQ TXRDY - EP6RST EP5RST EP4RST - EP6INT EP5INT EP4INT - EP6INTE EP5INTE EP4INTE FDAT7 FDAT6 FDAT5 FDAT4 AT89C5130A/31A KBLS4 KBLS3 KBLS2 KBLS1 STO SI AA CR1 SC1 SC0 - - SD4 SD3 SD2 SD1 ...

  • Page 26

    ... AUXR 8Eh Auxiliary Register 0 AUXR1 A2h Auxiliary Register 1 CKCON0 8Fh Clock Control 0 CKCON1 AFh Clock Control 1 LEDCON F1h LED Control FCON D1h Flash Control EECON D2h EEPROM Contol AT89C5130A/31A BYCT7 BYCT6 BYCT5 BYCT4 - - - - FNUM7 FNUM6 FNUM5 FNUM4 - - CRCOK CRCERR ...

  • Page 27

    ... GF3 This bit is a general-purpose user flag Always cleared. Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection 0 DPS Cleared to select DPTR0. Set to select DPTR1. AT89C5130A/31A-M External Data Memory GF3 DPS 27 ...

  • Page 28

    ... In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc- tion (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C5130A/31A-M 28 AUXR1 EQU 0A2H ...

  • Page 29

    ... Program/Code Memory The AT89C5130A/31A-M implement 16/ 32 Kbytes of on-chip program/code memory. Figure 8- 1 shows the split of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or ...

  • Page 30

    ... Table 8-1. 8.1.2 External Bus Cycles This section describes the bus cycles the AT89C5130A/31A-M executes to fetch code (see Figure 8-3) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri- ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode (see the clock Section) ...

  • Page 31

    ... Flash Memory Architecture AT89C5130A/31A-M features two on-chip Flash memories: • Flash memory FM0: containing 32 Kbytes of program memory (user space) organized into 128-byte pages, • Flash memory FM1: 3 Kbytes for bootloader and Application Programming Interfaces (API). The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the “ ...

  • Page 32

    ... FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the program- ming. This sequence is 5 followed by A. Table 8-3 summarizes the memory spaces to program according to FMOD1:0 bits. AT89C5130A/31A-M 32 FM0 Blocks Select Bits FMOD1 ...

  • Page 33

    ... Security Space Reserved A X Interrupts that may occur during programming time must be disabled to avoid any spurious exit of the idle mode. AT89C5130A/31A-M FMOD1 FMOD0 Operation action Write the column latches in user 0 0 space action Write the column latches in extra row ...

  • Page 34

    ... Disable the interrupts. • Launch the programming by writing the data sequence 52h followed by A2h in FCON register. The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. AT89C5130A/31A-M 34 Column Latches Loading Procedure Column Latches Column Latches Mapping DPTR = Address ...

  • Page 35

    ... The end of the programming indicated by the FBusy flag cleared. • Enable the interrupts. 4337K–USB–04/08 Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 8-5 Disable Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Erase Mode FCON = 00h End Programming Enable AT89C5130A/31A-M 35 ...

  • Page 36

    ... The following procedure is used to read the Extra Row space and is summarized in Figure 8-8: • Map the Extra Row space by writing 02h in FCON register. • Read one byte in Accumulator by executing MOVC A, @A+DPTR with & DPTR = FF80h to FFFFh. AT89C5130A/31A-M 36 Hardware Programming Procedure Flash Spaces ...

  • Page 37

    ... Clear to re-map the data memory space. Flash Mode 2-1 FMOD1:0 See Table 8-2 or Table 8-3. Flash Busy Set by hardware when programming is in progress. 0 FBUSY Clear by hardware when programming is done. Can not be cleared by software. AT89C5130A/31A-M FCON = 00000xx0b Data Read DPTR = Address ACC = 0 Erase Mode FCON = 00h FPL0 ...

  • Page 38

    ... The Flash may be programmed or erased in the end-user application by calling low- level routines through a common entry point in the Boot Flash. 3. The Flash may be programmed using the parallel method. The bootloader and the Application Programming Interface (API) routines are located in the Flash Bootloader. AT89C5130A/31A-M 38 pins of the microcontroller. CC 4337K–USB–04/08 ...

  • Page 39

    ... API or with the parallel programming modes. This page, called “Extra Flash Memory”, is not in the internal Flash program memory addressing space. 9.4.1 Hardware Registers The only hardware register of the AT89C5130A/31A-M is called Hardware Security Byte (HSB). Table 9-1. 9.4.1.1 Bootloader Jump Bit (BLJB) One bit of the HSB, the BLJB bit, is used to force the boot address: • ...

  • Page 40

    ... Array Flash. They are accessed in the following ways: • Commands issued by the parallel memory programmer. • Commands issued by the ISP software. • Calls of API issued by the application software. Several software registers are described in Table 9-3. AT89C5130A/31A-M 40 Program Lock bits Program Lock Bits Security level ...

  • Page 41

    ... Do not clear this bit. User Memory Lock Bits 1-0 LB1-0 See Table 9-5 AT89C5130A/31A-M Default value FFh – 0FFh – FFh – 58h Atmel C51 X2, Electrically D7h Erasable AT89C5130A/31A-M 32 F7h Kbyte AT89C5130A/31A-M 32 DFh Kbyte, revision 0 and Table 9-4 Table 9- LB1 LB0 41 ...

  • Page 42

    ... Flash Memory Status AT89C5130A/31A-M parts are delivered with the ISP boot in the Flash memory. After ISP or par- allel programming, the possible contents of the Flash memory are summarized in Figure 9-1. Flash Memory Possible Contents 3FFFh AT89C5130A-M 7FFFh AT89C5131A-M Virgin Application 0000h Default After ISP 9 ...

  • Page 43

    ... The following procedure is used to read the data stored in the EEPROM memory: • Set bit EEE of EECON register • Stretch the MOVX to accommodate the slow access time of the column latch (Set bit M0 of AUXR register) • Load DPTR with the address to read • Execute a MOVX A, @DPTR 4337K–USB–04/08 AT89C5130A/31A-M 43 ...

  • Page 44

    ... Registers Table 10-1. Reset Value = XXXX XX00b Not bit addressable AT89C5130A/31A-M 44 EECON (S:0D2h) EECON Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. Reserved 3 - The value read from this bit is indeterminate. Do not set this bit. ...

  • Page 45

    ... In-System Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technol- ogy the AT89C5130A/31A-M allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer pro- gram at any stages of a product’ ...

  • Page 46

    ... The default value of SBV is FFh (no user boot loader in FM0 read or modify this byte, the APIs are used. Extra Byte (EB) & Boot Status Byte (BSB): - These Bytes are reserved for customer use read or modify these Bytes, the APIs are used. AT89C5130A/31A-M 46 F400h 7FFFh Custom ...

  • Page 47

    ... FM1 XROW Mapping Description Copy of the Manufacturer Code Copy of the Device ID#1: Family code Copy of the Device ID#2: Memories size and type AT89C5130A/31A-M bit ENBOOT in AUXR1 Register Is Initialized with BLJB Inverted. Example, if BLJB=0, ENBOOT is set (=1) during reset, thus the bootloader is executed after the reset ...

  • Page 48

    ... As PSEN is an output port in normal operating mode (running user application or bootloader code) after reset recommended to release PSEN after rising edge of reset signal. To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on (see AT89C5130A/31A-M 48 Description Copy of the Device ID#3: Name and Revision ...

  • Page 49

    ... BLJB can always be changed by the means of API, whether it's a low or high pin count pack- age.But for a low pin count version, if BLJB=1, no ISP via the Bootloader is further possible (because the HW conditions are never evaluated, as described in the USB Bootloader Datasheet back to ISP, BLJB needs to be changed by a parallel programmer(or by the APIs). AT89C5130A/31A-M 49 ...

  • Page 50

    ... AT89C5130A/31A-M devices have expanded RAM in external data space; maximum size and location are described in Table 12-1. Table 12-1. The AT89C5130A/31A-M has on-chip data memory which is mapped into the following four sep- arate segments. 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable ...

  • Page 51

    ... Number Mnemonic Description Disable Weak Pull Up 7 DPU Cleared to enabled weak pull up on standard Ports. Set to disable weak pull up on standard Ports. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit AT89C5130A/31A XRS1 XRS0 EXTRAM ...

  • Page 52

    ... Reset Value = 0X0X 1100b Not bit addressable AT89C5130A/31A-M 52 Bit Bit Number Mnemonic Description Pulse length Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock 5 M0 periods (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. ...

  • Page 53

    ... Timer 2 The Timer 2 in the AT89C5130A/31A-M is the standard C52 Timer 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2 controlled by T2CON (Table 13-1) and T2MOD (Table 13-2) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. ...

  • Page 54

    ... Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. • Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. • To start the timer, set TR2 run control bit in T2CON register. AT89C5130A/31A ...

  • Page 55

    ... RCAP2H and RCAP2L registers. Figure 13-2. Clock-out Mode C/ 4337K–USB–04/08 F CLK PERIPH T2 T2EX AT89C5130A/31A-M TR2 T2CON TH2 TL2 (8-bit) (8-bit) RCAP2H RCAP2L ...

  • Page 56

    ... Table 13-1. 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT89C5130A/31A-M 56 T2CON Register T2CON - Timer 2 Control Register (C8h EXF2 RCLK TCLK Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. ...

  • Page 57

    ... The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. AT89C5130A/31A T2OE 0 DCEN ...

  • Page 58

    ... The PCA timer is a common time base for all five modules (see Figure 14-1). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 14-1) and can be programmed to run at: • 1/6 the • 1/2 the • The Timer 0 overflow • The input on the ECI pin (P1.2) AT89C5130A/31A-M 58 ÷ ) CLK PERIPH ÷ ) ...

  • Page 59

    ... CPS0 1 0 Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = f PCA Enable Counter Overflow Interrupt ECF Cleared to disable CF bit in CCON to inhibit an interrupt. Set to enable CF bit in CCON to generate an interrupt. AT89C5130A/31A-M To PCA modules overflow Bit Up Counter CMOD ECF 0xD9 CCON 0xD8 ...

  • Page 60

    ... These flags can only be cleared by software. Table 14- Bit Number AT89C5130A/31A-M 60 CCON Register CCON - PCA Counter Control Register (D8h – CCF4 Bit Mnemonic Description PCA Counter Overflow flag CF Set by hardware when the counter rolls over ...

  • Page 61

    ... PCA Module 1 Interrupt Flag CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 Interrupt Flag CCF0 Must be cleared by software. Set by hardware when a match or capture occurs CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 AT89C5130A/31A-M CCON 0xD8 To Interrupt priority decoder IE.6 IE ...

  • Page 62

    ... CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh) CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh) CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh) CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh Bit Number AT89C5130A/31A-M 62 CCAPMn Registers ( ECOMn CAPPn CAPNn MATn Bit Mnemonic Description Reserved - The value read from this bit is indeterminate ...

  • Page 63

    ... CCAPnH Registers ( Bit Mnemonic Description PCA Module n Compare/Capture Control - CCAPnH Value AT89C5130A/31A-M PWMm ECCFn Module Function Operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger CEXn 16-bit capture by a transition on ...

  • Page 64

    ... Bit Number Reset Value = 0000 0000b Not bit addressable Table 14- PCA Counter Register Low (0E9h Bit Number Reset Value = 0000 0000b Not bit addressable AT89C5130A/31A-M 64 CCAPnL Registers ( Bit Mnemonic Description PCA Module n Compare/Capture Control - CCAPnL Value CH Register ...

  • Page 65

    ... CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 14-4). 4337K–USB–04/08 CR CCF4 CCF3 CCF2 CCF1 CCF0 Capture CAPPn CAPNn MATn TOGn PWMn ECCFn AT89C5130A/31A-M CCON 0xD8 PCA IT PCA Counter/Timer CH CL CCAPnH ...

  • Page 66

    ... PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see Figure 14-5). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. AT89C5130A/31A ...

  • Page 67

    ... The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. 4337K–USB–04/ CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16-bit Comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn AT89C5130A/31A-M CCON 0xD8 PCA IT CEXn CCAPMn 0xDA to 0xDE 67 ...

  • Page 68

    ... Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. AT89C5130A/31A-M 68 CCAPnH ...

  • Page 69

    ... Serial I/O Port The serial I/O port in the AT89C5130A/31A-M is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates ...

  • Page 70

    ... To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b Slave B:SADDR1111 0011b AT89C5130A/31A-M 70 RXD ...

  • Page 71

    ... XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. 4337K–USB–04/08 SADEN1111 1101b Given1111 00X1b SADDR0101 0110b SADEN1111 1100b SADEN1111 1010b Broadcast1111 1X11b, SADEN1111 1001b Broadcast1111 1X11B, SADEN1111 1101b Broadcast1111 1111b AT89C5130A/31A-M 71 ...

  • Page 72

    ... Reset Value = 0000 0000b Not bit addressable 15.3 Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 15-4. Baud Rate Selection AT89C5130A/31A ...

  • Page 73

    ... SMOD1 2 (BRL) = 256 - (1-SPD Baud_Rate SCON Register – SCON Serial Control Register (98h SM1 SM2 REN AT89C5130A/31A-M Clock Source Clock Source UART Tx UART Rx Timer 1 Timer 2 Timer 1 Timer 2 INT_BRG INT_BRG Timer 1 INT_BRG Timer 2 INT_BRG INT_BRG ...

  • Page 74

    ... Reset Value = 0000 0000b Bit addressable AT89C5130A/31A-M 74 Bit Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. FE Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection ...

  • Page 75

    ... F = 16.384 MHz OSC BRL 4800 247 2400 238 1200 220 600 185 6 5 – – – – – – AT89C5130A/31A-M F OSC Error (%) BRL 1.23 243 1.23 230 1.23 217 1.23 204 0.63 178 0.31 100 1. OSC Error (%) BRL 1.23 243 1.23 230 1.23 202 ...

  • Page 76

    ... Reset Value = 0000 0000b Table 15-2. T2CON - Timer 2 Control Register (C8h) 7 TF2 Bit Number Reset Value = 0000 0000b Bit addressable AT89C5130A/31A – – – T2CON Register EXF2 RCLK TCLK Bit Mnemonic Description Timer 2 overflow Flag TF2 Must be cleared by software ...

  • Page 77

    ... Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode Bit IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. BDRCON Register BRR AT89C5130A/31A GF1 GF0 PD rises from 0 to its nominal voltage. Can also be set TBCK RBCK ...

  • Page 78

    ... Number Reset Value = XXX0 0000b Not bit addressable AT89C5130A/31A-M 78 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit Reserved - The value read from this bit is indeterminate. Do not set this bit Reserved - The value read from this bit is indeterminate ...

  • Page 79

    ... Interrupt System 16.1 Overview The AT89C5130A/31A-M has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1. ...

  • Page 80

    ... Thus within each priority level there is a second priority structure determined by the polling sequence. Table 16-2. IEN0 - Interrupt Enable Register (A8h AT89C5130A/31A-M 80 (Table 16-4). Table 16-1. shows the bit values and priority levels associated with Priority Level Bit Values IPH.x IPL ...

  • Page 81

    ... Timer 0 overflow interrupt Enable bit ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. IPL0 Register PPCL PT2L PSL AT89C5130A/31A PT1L PX1L PT0L 0 PX0L 81 ...

  • Page 82

    ... Reset Value = X000 0000b Bit addressable Table 16-4. IPH0 - Interrupt Priority High Register (B7h AT89C5130A/31A-M 82 Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit PPCL Refer to PPCH for priority level. ...

  • Page 83

    ... PX1H Highest Timer 0 overflow interrupt Priority High bit PT0H PT0L Priority Level 0 0 Lowest PT0H Highest External interrupt 0 Priority High bit PX0H PX0L Priority Level 0 0 Lowest PX0H Highest IEN1 Register AT89C5130A/31A-M 83 ...

  • Page 84

    ... IEN1 - Interrupt Enable Register (B1h Bit Number AT89C5130A/31A EUSB - - Bit Mnemonic Description - Reserved USB Interrupt Enable bit EUSB Cleared to disable USB interrupt. Set to enable USB interrupt. - Reserved - Reserved - Reserved SPI interrupt Enable bit ESPI Cleared to disable SPI interrupt. ...

  • Page 85

    ... The value read from this bit is indeterminate. Do not set this bit. SPI Interrupt Priority bit PSPIL Refer to PSPIH for priority level. TWI Interrupt Priority bit PTWIL Refer to PTWIH for priority level. Keyboard Interrupt Priority bit PKBL Refer to PKBH for priority level. AT89C5130A/31A PSPIL PTWIL PKBDL 0 85 ...

  • Page 86

    ... IPH1 - Interrupt Priority High Register (B3h Bit Number Reset Value = X0XX X000b Not bit addressable AT89C5130A/31A-M 86 IPH1 Register PUSBH - - Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. USB Interrupt Priority High bit ...

  • Page 87

    ... Timer PCA 8 8 Keyboard 9 9 TWI 10 10 SPI USB 15 15 AT89C5130A/31A-M Vector Interrupt Request Address 0000h IE0 0003h TF0 000Bh IE1 0013h IF1 001Bh RI+TI 0023h TF2+EXF2 002Bh CF + CCFn (n = 0-4) 0033h KBDIT 003Bh TWIIT 0043h SPIIT 004Bh ...

  • Page 88

    ... Keyboard Interface 17.1 Introduction The AT89C5130A/31A-M implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes. ...

  • Page 89

    ... Cleared by hardware when reading KBF SFR by software. Keyboard line 0 flag Set by hardware when the Port line 0 detects a programmed level. It generates a KBF0 Keyboard interrupt request if the KBIE.0 bit in KBIE register is set. Cleared by hardware when reading KBF SFR by software. AT89C5130A/31A KBF3 KBF2 ...

  • Page 90

    ... Table 17-2. KBE - Keyboard Input Enable Register (9Dh) 7 KBE7 Bit Number Reset Value = 0000 0000b AT89C5130A/31A-M 90 KBE Register KBE6 KBE5 KBE4 Bit Mnemonic Description Keyboard line 7 Enable bit KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. ...

  • Page 91

    ... Keyboard line 1 Level Selection bit KBLS1 Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. AT89C5130A/31A KBLS3 KBLS2 KBLS1 0 ...

  • Page 92

    ... Programmable LED AT89C5130A/31A-M have programmable LED current sources, configured by the regis- ter LEDCON. Table 18-1. LEDCON (S:F1h) LED Control Register 7 Bit Number 7:6 5:4 3:2 1:0 Reset Value = 00h AT89C5130A/31A-M 92 LEDCON Register LED3 LED2 Bit Mnemonic Description Port LED3 Configuration 0 0 Standard C51 Port ...

  • Page 93

    ... Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. 4337K–USB–04/08 shows a typical SPI bus configuration using one Master controller and many Slave MISO MOSI SCK SS VDD Master Slave 4 AT89C5130A/31A-M Slave 1 Slave 3 Slave 2 93 ...

  • Page 94

    ... AT89C5130A/31A Clearing SSDIS control bit does not clear MODF. 2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this mode, the SS is used to start the transmission. gives the different clock rates selected by SPR2:SPR1:SPR0: ...

  • Page 95

    ... SPI module. FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS MSTR SPI Interrupt Request SPIF AT89C5130A/31A-M Clock Rate Baud Rate Divisor (BD) Don’t Use No BRG Internal Bus SPDAT Shift Register Receive Data Register Pin ...

  • Page 96

    ... SPCON: the Clock POLarity (CPOL the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the AT89C5130A/31A-M 96 8-bit Shift Register MOSI SPI Clock Generator Master MCU The SPI module should be configured as a Master before it is enabled (SPEN set) ...

  • Page 97

    ... MSB bit6 bit5 bit4 bit3 Byte 1 Byte 2 Figure 19-5, the first SCK edge is the MSB capture strobe. Therefore the Slave shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driv- AT89C5130A/31A bit2 bit1 LSB bit2 bit1 LSB 6 ...

  • Page 98

    ... Flag SPIF (SP Data Transfer) MODF (Mode Fault) Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. AT89C5130A/31A-M 98 SPI Interrupts Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = “0”) ...

  • Page 99

    ... MSTR Cleared to configure the SPI as a Slave. Set to configure the SPI as a Master. Clock Polarity CPOL Cleared to have the SCK set to “0” in idle state. Set to have the SCK set to “1” in idle state. AT89C5130A/31A-M SPI CPU Interrupt Request CPOL ...

  • Page 100

    ... SPSTA - Serial Peripheral Status and Control register (0C4H) 7 SPIF Bit Number AT89C5130A/31A-M 100 Bit Mnemonic Description Clock Phase CPHA Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). ...

  • Page 101

    ... The value read from this bit is indeterminate. Do not set this bit. Reserved - The value read from this bit is indeterminate. Do not set this bit. (Table 19- read/write buffer for the receive data regis- SPDAT Register AT89C5130A/31A 101 ...

  • Page 102

    ... ICs connected to them. The serial data transfer is limited to 400 Kbit/s in standard mode. Various communication configuration can be designed using this bus. 20-1 shows a typical 2-wire bus configuration. All the devices connected to the bus can be mas- ter and slave. Figure 20-1. 2-wire Bus Configuration SCL SDA AT89C5130A/31A-M 102 ) TWI ... device1 device2 device3 ...

  • Page 103

    ... Address Register SSADR Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status Status Decoder Bits Status Register SSCS AT89C5130A/31A-M 8 ACK CLK PERIPH Interrupt 7 8 103 ...

  • Page 104

    ... Slave receiver Data transfer in each mode of operation is shown in Table to Table 20-9 and Figure 20-4. to Figure 20-7.. These figures contain the following abbreviations START condition AT89C5130A/31A-M 104 Table 20-11), the Synchronous Serial Control and Status register (SSCS; shows how a data transfer is accomplished on the 2-wire bus. ...

  • Page 105

    ... The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave 4337K–USB–04/08 SSCON Initialization SSIE STA STO AT89C5130A/31A CR1 CR0 0 X bit rate bit rate 105 ...

  • Page 106

    ... While AA is reset, the TWI module does not respond to its own slave address. However, the 2-wire bus is still monitored and address recognition may be resume at any time by setting AA. This means that the AA bit may be used to temporarily isolate the module from the 2-wire bus. AT89C5130A/31A-M 106 SSADR: Slave Receiver Mode Initialization A5 ...

  • Page 107

    ... SDA and SLC must be set to logic 1. Table 20-4. CR2 CR1 CR0 4337K–USB–04/08 Bit Frequency Configuration Bit Frequency ( kHz MHz MHz OSCA OSCA 47 62.5 53.5 71.5 62 100 AT89C5130A/31A-M F divided by OSCA 256 224 192 160 107 ...

  • Page 108

    ... CR2 CR1 CR0 AT89C5130A/31A-M 108 Bit Frequency ( kHz MHz MHz OSCA OSCA - - 100 133.3 200 266.6 0.5 <. < 62.5 0.67 <. < divided by OSCA Unused 120 60 Timer 1 in mode 2 can be used as TWI baudrate generator with the following formula: 96.(256-” ...

  • Page 109

    ... A P 20h Other master continues 38h Other master A continues 68h 78h B0h Data A n AT89C5130A/31A 28h S SLA 10h A P 30h Other master continues 38h To corresponding states in slave mode Any number of data bytes and their associated acknowledge bits ...

  • Page 110

    ... Write data byte No SSDAT action Data byte has been 30h transmitted; NOT ACK No SSDAT action has been received No SSDAT action No SSDAT action Arbitration lost in 38h SLA+W or data bytes No SSDAT action AT89C5130A/31A-M 110 Application software response To SSCON SSSTA SSSTO SSI SSAA ...

  • Page 111

    ... Other master A continues 68h 78h B0h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C5130A/31A Data 58h S SLA R 10h W MT Other master A continues 38h To corresponding ...

  • Page 112

    ... Data byte has been 50h received; ACK has been returned Read data byte Read data byte Data byte has been Read data byte 58h received; NOT ACK has been returned Read data byte AT89C5130A/31A-M 112 Application software response To SSCON SSSTA SSSTO SSI SSAA ...

  • Page 113

    ... A 60h A 68h General Call A 70h A 78h Any number of data bytes and their associated Data A acknowledge bits This number (contained in SSCS) corresponds defined state of the 2-wire bus AT89C5130A/31A Data A Data A 80h 80h 88h Data Data A A 90h ...

  • Page 114

    ... Previously addressed with own SLA+W; data has been 88h received; NOT ACK has been returned Previously addressed with general call; data has been 90h received; ACK has been returned AT89C5130A/31A-M 114 Application Software Response To/from SSDAT To SSCON STA STO SI No SSDAT action or X ...

  • Page 115

    ... No SSDAT action SSDAT action AT89C5130A/31A-M AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if 1 GC=logic 1 Switched to the not addressed slave mode; no recognition of own SLA or GCA ...

  • Page 116

    ... Arbitration lost in SLA+R/W as master; own SLA+R has been B0h received; ACK has been returned Data byte in SSDAT has been B8h transmitted; NOT ACK has been received AT89C5130A/31A-M 116 A Data SLA R A8h A B0h Any number of data bytes and their associated Data ...

  • Page 117

    ... To/from SSDAT To SSCON STA STO No SSDAT action No SSCON action No SSDAT action 0 1 AT89C5130A/31A-M AA Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if 1 GC=logic 1 Switched to the not addressed slave mode ...

  • Page 118

    ... Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write) SD7 7 Bit Number AT89C5130A/31A-M 118 SSIE STA STO Bit Mnemonic Description Control Rate bit 2 CR2 See . Synchronous Serial Interface Enable bit SSIE Clear to disable SSLC. Set to enable SSLC. ...

  • Page 119

    ... Slave address bit 5. A4 Slave address bit 4. A3 Slave address bit 3. A2 Slave address bit 2. A1 Slave address bit 1. General call bit GC Clear to disable the general call address recognition. Set to enable the general call address recognition. AT89C5130A/31A SC0 ...

  • Page 120

    ... D- 21.1.1 Serial Interface Engine (SIE) The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and un-stuffing. • CRC generation and checking. • Handshakes. • TOKEN type identifying. AT89C5130A/31A-M 120 48 MHz +/- 0.25% DPLL 12 MHz SIE C51 Microcontroller Interface ...

  • Page 121

    ... NRZI ‘NRZ Bit Un-stuffing Packet Bit Counter Clock SysClk Recovery (12 MHz) USB Pattern Generator Parallel to Serial Converter Bit Stuffing NRZI Converter CRC16 Generator AT89C5130A/31A-M SYNC Detection PID Decoder DataOut Address Decoder 8 Serial CRC5 and CRC16 Generation/Check 8 DataIn [7:0] ...

  • Page 122

    ... The new address will be stored in the USBADDR reg- ister. The FEN bit and the FADDEN bit in the USBCON register will be set to allow the USB controller to answer only to requests sent at the new address. AT89C5130A/31A-M 122 Asynchronous Information ...

  • Page 123

    ... EPTYPE with the following values: – Control:EPTYPE = 00b – Isochronous:EPTYPE = 01b – Bulk:EPTYPE = 10b – Interrupt:EPTYPE = 11b 4337K–USB–04/08 UEPCON0 UEPDAT0 0 UBYCTL0 UEPCON6 UEPDAT6 UBYCTL6 UEPNUM AT89C5130A/31A-M SFR registers X UEPSTAX UEPCONX UEPDATX UBYCTHX UBYCTLX 123 ...

  • Page 124

    ... Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints. 21.3 Read/Write Data FIFO 21.3.1 FIFO Mapping Depending on the selected endpoint through the UEPNUM register, the UEPDATX register allows to access the corresponding endpoint data fifo. AT89C5130A/31A-M 124 Summary of Endpoint Configuration EPEN ...

  • Page 125

    ... Warning 2: Do not write more bytes than supported by the corresponding endpoint. 21.4 Bulk/Interrupt Transactions Bulk and Interrupt transactions are managed in the same way. 4337K–USB–04/08 UEPCON0 UEPDAT0 UBYCTH0 UBYCTL0 UEPCON6 UEPDAT6 UBYCTH6 UBYCTL6 AT89C5130A/31A-M 0 SFR registers UEPSTAX UEPCONX 3 UBYCTHX UBYCTLX 4 5 ...

  • Page 126

    ... If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct and the endpoint byte counter contains the number of bytes sent by the Host. AT89C5130A/31A-M 126 HOST ...

  • Page 127

    ... DATA1 (m Bytes) OUT ACK RXOUTB1 OUT DATA0 (p Bytes) ACK RXOUTB0 AT89C5130A/31A-M C51 Endpoint FIFO Bank 0 - Read Byte 1 Endpoint FIFO Bank 0 - Read Byte 2 Endpoint FIFO Bank 0 - Read Byte n Clear RXOUTB0 Endpoint FIFO Bank 1 - Read Byte 1 Endpoint FIFO Bank 1 - Read Byte 2 Endpoint FIFO Bank 1 - Read Byte m ...

  • Page 128

    ... STAX register is set by the USB controller. This triggers a USB interrupt if enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO with new data. The firmware will never write more bytes than supported by the endpoint FIFO. All USB retry mechanisms are automatically managed by the USB controller. AT89C5130A/31A-M 128 HOST UFI ...

  • Page 129

    ... TXCMPL IN DATA1 (m Bytes) ACK TXCMPL IN DATA0 (p Bytes) ACK AT89C5130A/31A-M C51 Endpoint FIFO Bank 0 - Write Byte 1 Endpoint FIFO Bank 0 - Write Byte 2 Endpoint FIFO Bank 0 - Write Byte n Set TXRDY Endpoint FIFO Bank 1 - Write Byte 1 Endpoint FIFO Bank 1 - Write Byte 2 Endpoint FIFO Bank 1 - Write Byte m ...

  • Page 130

    ... IN Zero Length Packet (see 128). To send a STALL handshake, see • For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page AT89C5130A/31A-M 130 “STALL Handshake” on page 133. “Bulk/Interrupt IN Transactions in Standard Mode” on page “ ...

  • Page 131

    ... FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firm- ware, the data sent by the Host on the bank 1 endpoint FIFO will be lost. The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new packet receipt. 4337K–USB–04/08 AT89C5130A/31A-M 131 ...

  • Page 132

    ... The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still enabled, but all the USB registers are reset by hardware. The firmware will clear the EORINT bit to allow the next USB reset detection. AT89C5130A/31A-M 132 4337K–USB–04/08 ...

  • Page 133

    ... The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSP- CLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake- up event is detected. 4337K–USB–04/08 AT89C5130A/31A-M 133 ...

  • Page 134

    ... USB controller from its Suspend mode. The USB controller is then re-activated. Figure 21-11. Example of a Suspend/Resume Management 21.8.3 Upstream Resume A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up purpose. AT89C5130A/31A-M 134 Detection of a SUSPEND State WUPCPU Detection of a RESUME State USB Controller Init SPINT ...

  • Page 135

    ... SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND State Upstream RESUME Sent 21.9 Detach Simulation In order to be re-enumerated by the Host, the AT89C5130A/31A-M has the possibility to simu- late a DETACH - ATTACH of the USB bus. The V REF up as shown in set the USBCON register. Maintaining this output in high impedance for more than 3 µs will simulate the disconnection of the device ...

  • Page 136

    ... Figure 21-14. Disconnect Timing D+ V (min) IHZ Disconnected 21.10 USB Interrupt System 21.10.1 Interrupt System Priorities Figure 21-15. USB Interrupt Control System D+ USB Controller D- Table 21-2. AT89C5130A/31A-M 136 Connection REF V REF D- D+ AT89C5131 > = 2,5 ms Disconnect Device Detected EUSB EA IE1.6 IE0.7 Interrupt Enable Priority Levels IPHUSB ...

  • Page 137

    ... Register USBIEN (S:BEh) USB Global 141.). This bit is set by hardware when a USB resume is (See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt 141.). This bit is set by hardware when a USB suspend is detected AT89C5130A/31A-M 144). This bit is set by hardware Table 21-9 on page 144). This bit is set by Table 21-9 on 144) ...

  • Page 138

    ... Figure 21-16. USB Interrupt Control Block Diagram Endpoint 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 AT89C5130A/31A-M 138 EPXINT UEPINT.X EPXIE UEPIEN.X EUSB IE1.6 4337K–USB–04/08 ...

  • Page 139

    ... This bit will be set by the device firmware after a successful status phase of a SET_ADDRESS transaction. FADDEN It will not be cleared afterwards by the device firmware cleared by hardware on hardware reset or when an USB reset is received (see above). When this bit is cleared, the default function address is used (0). AT89C5130A/31A UPRSM RMWUPE ...

  • Page 140

    ... Table 21- Bit Number 7 Reset Value = 00h AT89C5130A/31A-M 140 USBINT Register USBINT (S:BDh) USB Global Interrupt Register WUPCPU EORINT Bit Mnemonic Description Reserved - The value read from these bits is always 0. Do not set these bits. Wake Up CPU Interrupt This bit is set by hardware when the USB controller is in SUSPEND state and is re- activated by a non-idle signal FROM USB line (not by an upstream resume) ...

  • Page 141

    ... The value read from these bits is always 0. Do not set these bits. - Enable Suspend Interrupt Set this bit to enable Suspend Interrupts (see the ESPINT (S:BEh) USB Global Interrupt Enable Register” on page Clear this bit to disable Suspend Interrupts. AT89C5130A/31A ESOFINT - - (See “ ...

  • Page 142

    ... Table 21-6. 7 FEN Bit Number 7 6-0 Reset Value = 80h Table 21- Bit Number 7-4 3-0 Reset Value = 00h AT89C5130A/31A-M 142 USBADDR Register USBADDR (S:C6h) USB Address Register UADD6 UADD5 UADD4 Bit Mnemonic Description Function Enable FEN Set this bit to enable the address filtering function. Cleared this bit to disable the function. ...

  • Page 143

    ... This bit has no effect for Control endpoints. Endpoint Type Set this field according to the endpoint configuration (Endpoint 0 will always be configured as control): EPTYPE[1:0] 00Control endpoint 01Isochronous endpoint 10Bulk endpoint 11Interrupt endpoint EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) AT89C5130A/31A DTGL EPDIR EPTYPE1 1 0 EPTYPE0 ...

  • Page 144

    ... Control, Bulk and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled (see“UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register” on page This bit will be cleared by the device firmware before setting TXRDY. Reset Value = 00h AT89C5130A/31A-M 144 UEPSTAX (S:CEh) USB Endpoint X Status Register 6 5 ...

  • Page 145

    ... UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High BYCT[7:0] Register EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number) (see Figure 21-11 on page 145). This byte count is equal to the number of data bytes received after the Data PID. NUM (S:C7h) USB Endpoint Number) AT89C5130A/31A FDAT3 FDAT2 ...

  • Page 146

    ... Table 21-12. UBYCTHX Register 7 - Bit Number 7-2 2-0 Reset Value = 00h AT89C5130A/31A-M 146 UBYCTHX (S:E3h) USB Byte Count High Register EPNUM set in UEPNUM Register UEP Bit Mnemonic Description Reserved - The value read from these bits is always 0. Do not set these bits. Byte Count MSB Most Significant Byte of the byte count of a received data packet ...

  • Page 147

    ... Endpoint 0 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset EP0RST or when an USB bus reset has been received. Then, clear this bit to complete the reset operation and start using the FIFO. AT89C5130A/31A EP3RST ...

  • Page 148

    ... Table 21-14. UEPINT Register 7 - Bit Number Reset Value = 00h AT89C5130A/31A-M 148 UEPINT (S:F8h read-only) USB Endpoint Interrupt Register EP6INT EP5INT EP4INT Bit Mnemonic Description Reserved - The value read from this bit is always 0. Do not set this bit. ...

  • Page 149

    ... Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. Endpoint 0 Interrupt Enable EP0INTE Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. AT89C5130A/31A EP3INTE EP2INTE ...

  • Page 150

    ... Number 2-0 Reset Value = 00h Table 21-17. UFNUML Register 7 FNUM7 Bit Number Reset Value = 00h AT89C5130A/31A-M 150 UFNUMH (S:BBh, read-only) USB Frame Number High Register CRCOK CRCERR Bit Mnemonic Description Frame Number CRC OK This bit is set by hardware when a new Frame Number in Start of Frame Packet is CRCOK received without CRC error ...

  • Page 151

    ... The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-up resistor allowing power-on reset by simply connect- ing an external capacitor to V characteristics are discussed in the Section “DC Characteristics” of the AT89C5130A/31A-M datasheet. Figure 22-2. Reset Circuitry and Power-On Reset 22 ...

  • Page 152

    ... Figure 22-3. Recommended Reset Output Schematic AT89C5130A/31A-M 152 VDD RST RST AT89C5131A-M 1K VSS + VSS To other on-board circuitry 4337K–USB–04/08 ...

  • Page 153

    ... Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail Detect threshold level, the Reset will be applied immediately. AT89C5130A/31A-M CPU core Regulated ...

  • Page 154

    ... The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted. If the internal power supply falls below a safety level, a reset is immediately asserted. . AT89C5130A/31A-M 154 t 4337K–USB–04/08 ...

  • Page 155

    ... In this case, the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put AT89C5130A/31A-M into power-down mode. 4337K–USB–04/08 AT89C5130A/31A-M can be lowered to save further power ...

  • Page 156

    ... Mode Idle Idle Power-down Power-down Note: AT89C5130A/31A-M 156 Power-down Phase Oscillator restart Phase If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. ...

  • Page 157

    ... Cleared by software for general-purpose usage. Power-down mode bit PD Set this bit to enter in power-down mode. Cleared by hardware when reset occurs. Idle mode bit IDL Set this bit to enter in Idle mode. Cleared by hardware when interrupt or reset occurs. AT89C5130A/31A GF1 GF0 PD 0 IDL ...

  • Page 158

    ... Table 25-2. Table 25- Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C5130A/31A-M 158 = 1 make the best use of the WDT, it should be serviced in those sec- CLK PERIPH 7 counter has been added to extend the Time-out capability MHz ...

  • Page 159

    ... WDT just before entering power-down. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C5130A/31A-M while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...

  • Page 160

    ... AUXR - Auxiliary Register (8Eh) 7 DPU Bit Number Reset Value = 0X0X 1100b Not bit addressable AT89C5130A/31A-M 160 AUXR Register Bit Mnemonic Description Disable Weak Pull Up DPU Cleared to enabled weak pull up on standard Ports Set to disable weak pull up on standard Ports ...

  • Page 161

    ... CCIDLE I = 0.8xF(MHz)+15 CCwrite AT89C5130A/31A-M Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied ...

  • Page 162

    ... Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. Figure 27-1. I Figure 27-2. I AT89C5130A/31A-M 162 . I would be slightly higher if a crystal oscillator used (see Figure RST = V (see Figure 27-2 must be externally limited as follows: OL may exceed the related specification ...

  • Page 163

    ... ± 20 BUS GND 3 2 USB “B” Receptacle 1.5 kΩ 27Ω pad AT89C5130A/31A-M CC All other pins are disconnected. Tests in Active and Idle Modes CC 0.7V CC 0.2V -0 CLCH = T = 5ns. CHCL Typ Max Unit Test Conditions ...

  • Page 164

    ... To calculate each AC symbols. take the x value and use this value in the formula. Example 170 ns CCIV AT89C5130A/31A-M 164 Parameter USB Reference Voltage Input High Voltage for D+ and D- (Driven) Input High Voltage for D+ and D- (Floating) Input Low Voltage for D+ and D- Output High Voltage for D+ and D- Output Low Voltage for D+ and D- = Time for Address Valid to ALE Low ...

  • Page 165

    ... PSEN Low to Address Float AC Parameters for a Fix Clock ( MHz) Symbol Min LHLL T 10 AVLL T 10 LLAX T LLIV T 15 LLPL T 55 PLPH T PLIV T 0 PXIX T PXIZ T AVIV T PLAZ AT89C5130A/31A-M Max Units 165 ...

  • Page 166

    ... Table 27-4. Symbol 27.4.3 External Program Memory Read Cycle T ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 AT89C5130A/31A-M 166 AC Parameters for a Variable Clock Standard Type Clock T Min LHLL T Min AVLL T Min LLAX T Max LLIV T Min LLPL T Min ...

  • Page 167

    ... AC Parameters for a Variable Clock ( MHz) Symbol Min T 130 RLRH T 130 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 50 LLWL T 75 AVWL T 10 QVWX T 160 QVWH T 15 WHQX T RLAZ T 10 WHLH AT89C5130A/31A-M Max Units ns ns 100 160 ns 165 ns 100 167 ...

  • Page 168

    ... Table 27-7. Symbol 27.4.5 External Data Memory Write Cycle ALE PSEN WR PORT 0 PORT 2 AT89C5130A/31A-M 168 AC Parameters for a Variable Clock Standard Type Clock T Min RLRH T Min WLWH T Max RLDV T Min x RHDX T Max RHDZ T Max LLDV T Max AVDV T Min ...

  • Page 169

    ... Min QVHX T Min XHQX T Min XHDX T Max XHDV AT89C5130A/31A-M T WHLH T RLRH T RHDZ T RHDX DATA IN Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge ...

  • Page 170

    ... AC inputs during testing are driven at V measurement are made at V 27.4.12 Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ±20 mA. AT89C5130A/31A-M 170 ...

  • Page 171

    ... INDICATES ADDRESS TRANSITIONS DPL OR Rt OUT FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION DPL OR Rt OUT DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION OLD DATA NEW DATA P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED AT89C5130A/31A-M STATE3 STATE4 STATE5 ...

  • Page 172

    ... Table 27-13. Memory AC Timing Symbol T SVRL T RLSX T BHBL T BHBL Figure 27-5. Flash Memory - ISP Waveforms Figure 27-6. Flash Memory - Internal Busy Waveforms AT89C5130A/31A-M 172 Signals PSEN, EA RST FBUSY Flag Vcc = 3.3V ± 10 -40 to +85°C A Parameter Input PSEN Valid to RST Edge Input PSEN Hold after RST Edge ...

  • Page 173

    ... Full-speed Data Rate 11.9700 Crossover Voltage 1.3 Source Jitter Total to Next -3.5 Transaction Source Jitter Total for Paired Transactions Receiver Jitter to Next -18.5 Transaction Receiver Jitter for Paired Transactions Signals Clock Data In Data Out AT89C5130A/31A-M Fall Time 10 Typ Max Unit 12.0300 Mb/s 2 ...

  • Page 174

    ... CLIX CHIX T T CLOV, CHOV CLOX CHOX Note: AT89C5130A/31A-M 174 = -40 to +85°C A Parameter Clock Period Clock High Time Clock Low Time SS Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge ...

  • Page 175

    ... CHCH T T CHCX CLCX T SLOV (1) SLAVE MSB OUT T T IVCH CHIX T T IVCL CLIX MSB IN 1. Not Defined but generally the LSB of the character which has just been received. AT89C5130A/31A-M T CLSH T CHSH T CLCH T CHCL T T CLOX CLOV T T CHOX CHOV (1) BIT 6 ...

  • Page 176

    ... MISO (output) Note: Figure 27-10. SPI Master Waveforms (SSCPHA (output) SCK (CPOL= 0) (output) SCK (CPOL= 1) (output) MOSI (input) MISO (output) handled by software using general purpose port pin. SS AT89C5130A/31A-M 176 T CHCH T T CHCX CLCX T T IVCH CHIX T T IVCL CLIX MSB IN BIT 6 ...

  • Page 177

    ... Supply Voltage 16 2.7 to 5.5V 16 2.7 to 5.5V 16 2.7 to 5.5V 32 2.7 to 5.5V 32 2.7 to 5.5V 32 2.7 to 5.5V AT89C5130A/31A-M Temperature Range Package Industrial & Green VQFP64 Industrial & Green QFN32 Industrial & Green PLCC52 Industrial & Green VQFP64 Industrial & Green QFN32 Industrial & Green PLCC52 Packing Tray & ...

  • Page 178

    ... Packaging Information 29.1 64-lead VQFP AT89C5130A/31A-M 178 4337K–USB–04/08 ...

  • Page 179

    ... DATUM "A" AND "D" DETERMINED AT DATUM PLANE H. 6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE " f " DIMENSION AT MAXIMUM MATERIAL CONDITION . DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. 4337K–USB–04/08 AT89C5130A/31A-M 179 ...

  • Page 180

    ... PLCC STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE. AT89C5130A/31A-M 180 4337K–USB–04/08 ...

  • Page 181

    ... QFN 4337K–USB–04/08 AT89C5130A/31A-M 181 ...

  • Page 182

    ... AT89C5130A/31A-M 182 4337K–USB–04/08 ...

  • Page 183

    ... Changes from 4337I to 4337J 1. Removed non ‘Green’ part numbers from ordering information on page 177. 30.5 Changes from 4337J to 4337K 1. Corrected package drawing 4337K–USB–04/08 AT89C5130A/31A-M See “Two Wire Interface (TWI)” on page 102. “32-lead QFN” on page 181. page 48. ...

  • Page 184

    Description ............................................................................................... 2 2 Block Diagram .......................................................................................... 3 3 Pinout Description ................................................................................... 4 3.1 Pinout ................................................................................................................4 3.2 Signals ...............................................................................................................6 4 Typical Application ................................................................................ 12 4.1 Recommended External components .............................................................12 4.2 PCB Recommandations ..................................................................................13 5 Clock Controller ..................................................................................... 14 5.1 ...

  • Page 185

    ... Serial I/O Port ......................................................................................... 69 15.1 Framing Error Detection ..................................................................................69 15.2 Automatic Address Recognition ......................................................................70 15.3 Baud Rate Selection for UART for Mode 1 and 3 ............................................72 15.4 UART Registers ...............................................................................................75 16 Interrupt System ..................................................................................... 79 16.1 Overview ..........................................................................................................79 16.2 Registers .........................................................................................................80 16.3 Interrupt Sources and Vector Addresses .........................................................87 17 Keyboard Interface ................................................................................. 88 17.1 Introduction ......................................................................................................88 17.2 Description .......................................................................................................88 17.3 Registers .........................................................................................................89 18 Programmable LED ................................................................................ 92 4337K–USB–04/08 AT89C5130A/31A-M ii ...

  • Page 186

    ... Reset Output .................................................................................................151 23 Power Monitor ...................................................................................... 153 23.1 Description .....................................................................................................153 24 Power Management ............................................................................. 155 24.1 Idle Mode .......................................................................................................155 24.2 Power-down Mode .........................................................................................155 24.3 Registers .......................................................................................................157 25 Hardware Watchdog Timer .................................................................. 158 25.1 Using the WDT ..............................................................................................158 25.2 WDT During Power-down and Idle ................................................................159 26 Reduced EMI Mode .............................................................................. 160 AT89C5130A/31A-M iii 4337K–USB–04/08 ...

  • Page 187

    ... VQFP ................................................................................................178 29.2 52-lead PLCC ................................................................................................180 29.3 32-lead QFN ..................................................................................................181 30 Datasheet Revision History ................................................................. 183 30.1 Changes from 4337F to 4337G .....................................................................183 30.2 Changes from 4337G to 4337H .....................................................................183 30.3 Changes from 4337H to 4337I ......................................................................183 30.4 Changes from 4337I to 4337J .......................................................................183 30.5 Changes from 4337J to 4337K ......................................................................183 4337K–USB–04/08 AT89C5130A/31A-M iv ...

  • Page 188

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...