DSPIC30F4012-20I/ML Microchip Technology, DSPIC30F4012-20I/ML Datasheet - Page 28

• Manufacturer Part Number: DSPIC30F4012-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F401220IML

dsPIC30F4011/4012
FIGURE 3-4:
3.1.2
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically con-
tain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. For
information on instruction encoding, refer to the “16-bit
MCU and DSC Programmer’s Reference Manual”
(DS70157).
DS70135G-page 28
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Figure
PC Address
0x000004
0x000006
0x000000
0x000002
PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)
3-5), only the lower 16 bits of the
Section 2.4 “DSP
00000000
00000000
00000000
00000000
TBLRDH.B (Wn<0> = 1)
23
Note that by incrementing the PC by 2 for each
program memory word, the Least Significant 15 bits of
data space addresses directly map to the Least
Significant 15 bits in the corresponding program space
addresses. The remaining bits are provided by the
Program Space Visibility Page register, PSVPAG<7:0>,
as shown in
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions require one instruction
• All other instructions require two instruction cycles
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances require two instruction
• Any other iteration of the REPEAT loop allows the
16
Note:
cycle in addition to the specified execution time:
- MAC class of instructions with data operand
- MOV instructions
- MOV.D instructions
in addition to the specified execution time of the
instruction.
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
- Execution upon re-entering the loop after an
instruction, accessing data using PSV, to execute
in a single cycle.
TBLRDH.W
prefetch
interrupt
interrupt is serviced
TBLRDH.B (Wn<0> = 0)
PSV access is temporarily disabled during
table reads/writes.
Figure
8
3-5.
© 2010 Microchip Technology Inc.
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