AT89C51CC01UA-RLRUM Atmel, AT89C51CC01UA-RLRUM Datasheet - Page 139

• Manufacturer Part Number: AT89C51CC01UA-RLRUM
• Description: IC 8051 MCU 32K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: AT89C CANr

Specifications of AT89C51CC01UA-RLRUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1280 B
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: CANADAPT28
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AT89C51CC01UA-RLRUMTR

4129N–CAN–03/08
Table 116. IEN1 Register
IEN1 (S:E8h)
Interrupt Enable Register
Reset Value = xxxx x000b
bit addressable
Number
Bit
7
-
7
6
5
4
3
2
1
0
Mnemonic Description
EADC
ECAN
ETIM
Bit
6
-
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
TImer Overrun Interrupt Enable bit
Clear to disable the timer overrun interrupt.
Set to enable the timer overrun interrupt.
ADC Interrupt Enable bit
Clear to disable the ADC interrupt.
Set to enable the ADC interrupt.
CAN Interrupt Enable bit
Clear to disable the CAN interrupt.
Set to enable the CAN interrupt.
5
-
4
-
3
-
ETIM
2
EADC
1
ECAN
0
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