DSPIC30F4012-30I/SP Microchip Technology, DSPIC30F4012-30I/SP Datasheet - Page 110

• Manufacturer Part Number: DSPIC30F4012-30I/SP
• Description: IC DSPIC MCU/DSP 48K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012-30I/SP

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 20
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401230ISP

dsPIC30F4011/4012
16.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1 pin to
perform the frame synchronization pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
FIGURE 16-1:
FIGURE 16-2:
DS70135G-page 110
SDO1
SCK1
SDI1
Framed SPI Support
SS1
MSb
PROCESSOR 1
SPI BLOCK DIAGRAM
SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
SPI Master
SS1 and
FSYNC
Shift Register
Control
Receive
(SPI1BUF)
(SPI1SR)
SPI1BUF
Read
bit 0
SPI1SR
LSb
Control
Clock
SDO1
SCK1
SDI1
Clock
Shift
SPI1BUF
Write
Transmit
Data Bus
Internal
Serial Clock
Select
Edge
the SS1 pin is an input or an output (i.e., whether the
module receives or generates the frame synchroniza-
tion pulse). The frame pulse is an active-high pulse for
a single SPI clock cycle. When frame synchronization
is enabled, the data transmission starts only on the
subsequent transmit edge of the SPI clock.
SDI1
SDO1
SCK1
Enable Master Clock
1, 2, 4, 6, 8
Secondary
Prescaler
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPI1BUF)
(SPI1SR)
SPI Slave
© 2010 Microchip Technology Inc.
1, 4, 16, 64
Prescaler
Primary
LSb
F
CY