DSPIC30F5013-20E/PT Microchip Technology, DSPIC30F5013-20E/PT Datasheet - Page 7

• Manufacturer Part Number: DSPIC30F5013-20E/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5013-20E/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• For Use With: DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F5013-20EP

8. Module: Data Converter Interface – Idle
9. Module: 4x PLL Operation
EXAMPLE 8:
EXAMPLE 9:
EXAMPLE 10:
© 2008 Microchip Technology Inc.
.include
...
DISI#2 ; protect the disable of INT1
BCLRIEC1, #INT1IE; disable interrupt 1
...
.include
...
__asm__ volatile (“DISI #0x1FFF”);
SRbits.IPL = 0x5;
DISICNT = 0x0;
#define DISI_PROTECT(X) {\
DISI_PROTECT(SRbits.IPL = 0x5);
__builtin_writesfr(&U1MODE, reg_value);
where ‘reg_value’ is the 16-bit value to be
written to the SFR.
For this release of silicon, the DCI module should
not be stopped when the device enters Idle mode.
Work around
Do not set the DCISIDL (DCICON1<13>) bit. This
will ensure the DCI module continues to run when
the device enters Idle mode.
When the 4x PLL mode of operation is selected,
the specified input frequency range of 4-10 MHz is
not fully supported.
When device V
frequency must be in the range of 4-5 MHz. When
device V
must be in the range of 4-6 MHz for both industrial
and extended temperature ranges.
Work around
1. Use 8x PLL or 16x PLL mode of operation and
2. Use the EC without PLL Clock mode with a
__asm__ volatile (“DISI #0x1FFF”);\
X;
DISICNT = 0; }
set final device clock speed using the
POST<1:0> oscillator postscaler control bits
(OSCCON<7:6>).
suitable clock frequency to obtain the equivalent
4x PLL clock rate.
; next instruction protected by DISI
DD
is 3.0-3.6V, the 4x PLL input frequency
“p30fxxxx.inc”
“p30fxxxx.h”
USING DISI
RAISING CPU INTERRUPT PRIORITY LEVEL
USING MACRO
DD
is 2.5-3.0V, the 4x PLL input
\
// safely modify the CPU IPL
// protect CPU IPL modification
// set CPU IPL to 5
// remove DISI protection
10. Module: Interrupt Controller – Sequential
dsPIC30F5011/5013
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap. The
generic terms “Interrupt 1” and “Interrupt 2” are
used to represent any two enabled dsPIC30F
interrupts.
1. Interrupt 1 processing begins.
2. Interrupt 1 is negated by user software by one
3. Interrupt 2 occurs with a priority higher than
Work around
The user may disable interrupt nesting or execute
a DISI instruction before modifying the CPU IPL
or Interrupt 1 setting. A minimum DISI value of 2
is required if the DISI is executed immediately
before the CPU IPL or Interrupt 1 is modified, as
shown in Example 8. If the MPLAB C30 compiler
is being used, one must inspect the Disassembly
Listing in the MPLAB IDE file to determine the
exact number of cycles to disable level 1-6
interrupts. One may use a large DISI value and
then set the DISICNT register to zero, as shown in
Example 9. A macro may also be used to perform
this task, as shown in Example 10.
of the following methods:
- CPU IPL is raised to Interrupt 1 IPL level or
- Interrupt 1 IPL is lowered to CPU IPL level or
- Interrupt 1 is disabled (Interrupt 1 IE bit set to
- Interrupt 1 flag is cleared
Interrupt 1.
higher or
lower or
‘0’) or
Interrupts
DS80223H-page 7