AT90USB1287-MUR Atmel, AT90USB1287-MUR Datasheet - Page 172

• Manufacturer Part Number: AT90USB1287-MUR
• Description: MCU AVR 128K FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® 90USBr

Specifications of AT90USB1287-MUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90USBx
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATSTK525, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525, ATAVRQTOUCHX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17. Serial Peripheral Interface – SPI
172
AT90USB64/128
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
A T 9 0 U S B 6 4 / 1 2 8 a n d p e r i p h e r a l d e v i c e s o r b e tw e e n s e v e r a l A V R d e v i c e s . T h e
AT90USB64/128 SPI includes the following features:
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USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 206.
The Power Reduction SPI bit, PRSPI, in
page 50 must be written to zero to enable SPI module.
Figure 17-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
Figure 1-1 on page
(1)
3, and
“Power Reduction Register 0 - PRR0” on page 54
Table 10-6 on page 80
for SPI pin placement.
Figure
17-2. The sys-
7593K–AVR–11/09
on