PIC24FJ128GB206-I/PT Microchip Technology, PIC24FJ128GB206-I/PT Datasheet - Page 243

• Manufacturer Part Number: PIC24FJ128GB206-I/PT
• Description: MCU PIC 16BIT FLASH USB 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GB206-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 52
• Ram Memory Size: 96KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.3
The USB OTG module has many conditions that can
be configured to cause an interrupt. All interrupt
sources use the same interrupt vector.
Figure 18-9 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
U1IE and U1IR registers, respectively. The second
FIGURE 18-9:
 2010 Microchip Technology Inc.
USB Interrupts
CRC5EE (EOFEE)
CRC5EF (EOFEF)
Second Level (USB Error) Interrupts
CRC16EE
CRC16EF
DFN8EE
DFN8EF
DMAEF
DMAEE
BTOEE
BTOEF
BTSEF
BTSEE
PIDEE
PIDEF
Top Level (USB Status) Interrupts
USB OTG INTERRUPT FUNNEL
Top Level (USB OTG) Interrupts
PIC24FJ256GB210 FAMILY
URSTIE (DETACHIE)
URSTIF (DETACHIF)
level consists of USB error conditions, which are
enabled and flagged in the U1EIR and U1EIE registers.
An interrupt condition in any of these triggers a USB
Error Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 18-10 provides some common
events within a USB frame and their corresponding
interrupts.
RESUMEIF
RESUMEIE
ATTACHIE
ATTACHIF
SESENDIE
VBUSVDIE
T1MSECIF
SESENDIF
VBUSVDIF
(UERRIF)
TIMSECIE
LSTATEIE
LSTATEIF
STALLIE
STALLIF
SESVDIE
SESVDIF
UERRIE
ACTVIE
IDLEIE
ACTVIF
IDLEIF
TRNIE
SOFIE
TRNIF
SOFIF
IDIF
IDIE
Set USB1IF
DS39975A-page 243