DSPIC30F6012A-20E/PT Microchip Technology, DSPIC30F6012A-20E/PT Datasheet - Page 131

• Manufacturer Part Number: DSPIC30F6012A-20E/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The 20-bit mode treats each 256-bit AC-Link frame as
sixteen, 16-bit time slots. In the 20-bit AC-Link mode,
the module operates as if COFSG<3:0> = 1111 and
WS<3:0> = 1111. The data alignment for 20-bit data
slots is ignored. For example, an entire AC-Link data
frame can be transmitted and received in a packed
fashion by setting all bits in the TSCON and RSCON
SFRs. Since the total available buffer length is 64 bits,
it would take 4 consecutive interrupts to transfer the
AC-Link frame. The application software must keep
track of the current AC-Link frame segment.
18.7
The DCI module is configured for I
a value of ‘01’ to the COFSM<1:0> control bits in the
DCICON1 SFR. When operating in the I
DCI module will generate frame synchronization sig-
nals with a 50% duty cycle. Each edge of the frame
synchronization signal marks the boundary of a new
data word transfer.
The user must also select the frame length and data
word size using the COFSG and WS control bits in the
DCICON2 SFR.
© 2011 Microchip Technology Inc.
I
2
S Mode Operation
dsPIC30F6011A/6012A/6013A/6014A
2
S mode by writing
2
S mode, the
18.7.1
The WS and COFSG control bits are set to produce the
period for one half of an I
frame length is the total number of CSCK cycles
required for a left or a right data word transfer.
The BLEN bits must be set for the desired buffer length.
Setting BLEN<1:0> = 01 will produce a CPU interrupt,
once per I
18.7.2
As per the I
default, begin one CSCK cycle after a transition of the
WS signal. A MSb left justified option can be selected
using the DJST control bit in the DCICON1 SFR.
If DJST = 1, the I
tified. The MSb of the data word will be presented on
the CSDO pin during the same CSCK cycle as the ris-
ing or falling edge of the COFS signal. The CSDO pin
is tri-stated after the data word has been sent.
2
S frame.
2
I
LENGTH SELECTION
I
S specification, a data word transfer will, by
2
2
S FRAME AND DATA WORD
S DATA JUSTIFICATION
2
S data transfers will be MSb left jus-
2
S data frame. That is, the
DS70143E-page 131