DSPIC30F6012A-20E/PT Microchip Technology, DSPIC30F6012A-20E/PT Datasheet - Page 68

• Manufacturer Part Number: DSPIC30F6012A-20E/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F6011A/6012A/6013A/6014A
9.1
The 16-bit timer can be placed in the Gated Time
Accumulation mode. This mode allows the internal T
to increment the respective timer when the gate input
signal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2
The input clock (F
Timer has a prescale option of 1:1, 1:8, 1:64 and 1:256,
selected by control bits TCKPS<1:0> (T1CON<5:4>).
The prescaler counter is cleared when any of the
following occurs:
• A write to the TMR1 register
• A write to the T1CON register
• A device Reset, such as a POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
The TMR1 register is not cleared when the T1CON
register is written. It is cleared by writing to the TMR1
register.
9.3
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
• The TSYNC bit (T1CON<2>) is asserted to a logic
When all three conditions are true, the timer will con-
tinue to count up to the Period register and be reset to
0x0000.
When a match between the timer and the Period regis-
ter occurs, an interrupt can be generated if the
respective timer interrupt enable bit is asserted.
DS70143E-page 68
(TCS = 1) and
‘0’ which defines the external clock source as
asynchronous.
Timer Gate Operation
Timer Prescaler
Timer Operation During Sleep
Mode
OSC
/4 or external clock) to the 16-bit
CY
9.4
The 16-bit timer has the ability to generate an interrupt on
period match. When the timer count matches the Period
register, the T1IF bit is asserted and an interrupt will be
generated if enabled. The T1IF bit must be cleared in
software. The timer interrupt flag, T1IF, is located in the
IFS0 Control register in the interrupt controller.
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the respec-
tive timer interrupt enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
9.5
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time of day and event time-stamping
capabilities. Key operational features of the RTC are:
• Operation from 32 kHz LP oscillator
• 8-bit prescaler
• Low power
• Real-Time Clock interrupts
These Operating modes are determined by setting the
appropriate bit(s) in the T1CON Control register.
FIGURE 9-2:
C1 = C2 = 18 pF; R = 100K
C1
C2
Timer Interrupt
Real-Time Clock
32.768 kHz
XTAL
R
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
RTC
© 2011 Microchip Technology Inc.
SOSCI
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dsPIC30FXXXX