ATXMEGA256A3B-AU Atmel, ATXMEGA256A3B-AU Datasheet
ATXMEGA256A3B-AU
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ATXMEGA256A3B-AU Summary of contents
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... Board control Networking • • White Goods Optical ® ® TM AVR XMEGA Microcontroller 2 C and SMBus compatible) • Hand-held battery applications • Power tools • HVAC • Metering • Medical Applications 8/16-bit XMEGA A3B Microcontroller ATxmega256A3B Preliminary 8116I–AVR–09/10 ...
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... Ordering Information Ordering Code Flash ATxmega256A3B-AU 256 ATxmega256A3B-MH 256 Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green ...
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Pinout/Block Diagram Figure 2-1. Block diagram and pinout. INDEX CORNER PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND VCC PC0 Notes: 1. For full details on pinout and pin functions refer to 2. ...
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... The Bootloader software in the Boot Flash section will continue to run while the Appli- cation Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3B is a pow- erful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. 8116I– ...
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The XMEGA A3B devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 3.1 Block Diagram Figure 3-1. XMEGA A3B Block Diagram PA[0..7] PORT A (8) ...
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... The XMEGA application notes contain example code and show applied use of the modules and peripherals. The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr. 5. Disclaimer For devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology ...
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AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in SRAM • Stack Pointer accessible in I/O memory space • Direct ...
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The program memory is In- System Self-Programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with single clock cycle access time. ...
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Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...
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... Flash Program Memory (Hexadecimal address) 0 Application Section (256 KB) ... 1EFFF 1F000 Application Table Section (8 KB) 1FFFF 20000 Boot Section (8 KB) 20FFF Figure 7-2 on page Data Memory Map (Hexadecimal address) ATxmega256A3B 0 I/O Registers (4 KB) FFF XMEGA A3B 10. To simplify development, the memory map for 10 ...
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Figure 7-2. 7.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 ...
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... Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions. 8116I–AVR–09/10 Table 7-1 on page .Device ID bytes for XMEGA A3B device. Device Byte 2 ATxmega256A3B XMEGA A3B 12. The serial number consist of Device ID bytes Byte ...
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... Table 7-3. Devices EEPROM Size ATxmega256A3B 4 KB 8116I–AVR–09/10 shows the Flash Program Memory organization. Flash write and erase Number of words and Pages in the Flash. ...
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DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral • 4 Channels • From 1 ...
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Event System 9.1 Features • Inter-peripheral communication and signalling with minimum latency • CPU and DMA independent operation • 8 Event Channels allows for signals to be routed at the same time • Events can be ...
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Figure 9-1. The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com- munication Module (IRCOM). Events can also be generated from software (CPU). All ...
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System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...
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Figure 10-1. Clock system overview Internal Oscillator Calibrated Internal Run-Time Calibrated Internal Oscillator Run-time Calibrated Internal Oscillator Each clock source is briefly described in the following sub-sections. 10.3 Clock Options 10.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 ...
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Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 ...
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Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A3B provides various ...
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Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals ...
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System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – JTAG Reset – PDI reset – Software reset • Asynchronous ...
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JTAG reset The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details. 12.3.6 PDI reset ...
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Battery Backup System 13.1 Features • Battery Backup voltage supply from dedicated V – One Ultra Low-power 32-bit Real Time Counter – One 32.768 kHz crystal oscillator with failure detection monitor – Two Backup Registers • Typical power consumption ...
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Figure 13-1. Battery Backup Module and its power domain implementation Power VBAT supervisor (BBPOD, BBBOD, BBPWR) Failure TOSC1 Monitor XOSC TOSC2 RTC Backup Registers 8116I–AVR–09/10 Power Watchdog w/ switch independent RCOSC OCD & Programming Interface Peripherals Internal RAM XMEGA A3B ...
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PMIC - Programmable Multi-level Interrupt Controller 14.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...
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Table 14-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x040 NVM_INT_base 0x044 PORTB_INT_base 0x048 ACB_INT_base 0x04E ADCB_INT_base 0x056 PORTE_INT_base 0x05A TWIE_INT_base 0x05E TCE0_INT_base 0x06A TCE1_INT_base 0x074 USARTE0_INT_base 0x080 PORTD_INT_base 0x084 PORTA_INT_base 0x088 ACA_INT_base 0x08E ADCA_INT_base 0x09A TCD0_INT_base ...
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I/O Ports 15.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...
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Push-pull Figure 15-1. I/O configuration - Totem-pole 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) 15.3.4 Bus-keeper The bus-keeper’s weak output produces the ...
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down Figure 15-6. I/O configuration - Wired-AND with optional pull-up 8116I–AVR–09/10 DIRn OUTn INn OUTn INn INn OUTn XMEGA A3B Pn Pn ...
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Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure ...
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T/C - 16-bit Timer/Counter with PWM 16.1 Features • Seven 16-bit Timer/Counters – Four Timer/Counters of type 0 – Three Timer/Counters of type 1 • Four Compare or Capture (CC) Channels in Timer/Counter 0 • Two Compare or Capture ...
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Figure 16-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is ...
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AWEX - Advanced Waveform Extension 17.1 Features • Output with complementary output from each Capture channel • Four Dead Time Insertion (DTI) Units, one for each Capture channel • 8-bit DTI Resolution • Separate High and Low Side Dead-Time ...
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Hi-Res - High Resolution Extension 18.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 18.2 Overview ...
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RTC32 - 32-bit Real-Time Counter 19.1 Features • 32-bit resolution • One 32-bit Compare register • One 32-bit Period register • Clear Timer on overflow • Optional Interrupt/ Event on overflow and compare match • Selectable clock reference – ...
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TWI - Two Wire Interface 20.1 Features • Two Identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space ...
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SPI - Serial Peripheral Interface 21.1 Features • Two Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...
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USART 22.1 Features • Six Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...
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IRCOM - IR Communication Module 23.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed ...
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Crypto Engine 24.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • ...
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ADC - 12-bit Analog to Digital Converter 25.1 Features • Two ADCs with 12-bit resolution • 2 Msps sample rate for each ADC • Signed and Unsigned conversions • 4 result registers with individual input channel control for each ...
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Figure 25-1. ADC overview Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results ...
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DAC - 12-bit Digital to Analog Converter 26.1 Features • One DAC with 12-bit resolution • Msps conversion rate for each DAC • Flexible conversion range • Multiple trigger sources • 1 continuous output or 2 ...
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AC - Analog Comparator 27.1 Features • Four Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on ...
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Figure 27-1. Analog comparator overview Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled 8116I–AVR–09/10 XMEGA A3B + Pin 0 output AC0 - Interrupts Interrupt sensitivity control + AC1 ...
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Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 27-1 on page ...
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... Overview The XMEGA A3B has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s development tools - provides all the necessary functions to debug an application. It has support for program and data breakpoints, and can debug an application from C and high level language source code level, as well as assembler and disassembler level. It has full Non-Intru- sive Operation and no hardware or software resources in the device are used ...
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... TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and boundary scan. 29.4 PDI - Program and Debug Interface The PDI is an Atmel proprietary protocol for communication between the microcontroller and Atmel’s development tools. 8116I–AVR–09/10 XMEGA A3B ...
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Pinout and Pin Functions The pinout of XMEGA A3B is shown in I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate ...
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SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK 30.1.6 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT 30.1.7 Debug/System functions RESET PDI_CLK PDI_DATA TCK TDI TDO TMS 8116I–AVR–09/10 Serial Data In for TWI when external driver interface is enabled ...
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Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head ...
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Table 30-4. Port D - Alternate functions PORT D PIN # INTERRUPT GND 24 VCC 25 PD0 26 SYNC PD1 27 SYNC PD2 28 SYNC/ASYNC PD3 29 SYNC PD4 30 SYNC PD5 31 SYNC PD6 32 SYNC PD7 33 SYNC ...
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... PDI ATxmega256A3B Boundary Scan Order Signal Name PQ3.Bidir PQ3.Control PQ2.Bidir PQ2.Control PQ1.Bidir PQ1.Control PQ0.Bidir PQ0.Control PK7.Bidir PK7.Control PK6.Bidir PK6.Control PK5.Bidir PK5.Control PK4.Bidir PK4.Control PK3 ...
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Bit Number 109 108 107 106 105 104 103 102 101 100 ...
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Bit Number ...
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Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A3B. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Base Address 0x0000 0x0010 ...
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Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...
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Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...
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Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...
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Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear SBI A, b Set Bit in I/O Register ...
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Packaging information 33.1 64A PIN 0°~7° L Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...
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D Marked Pin TOP VIEW BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA ...
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Electrical Characteristics 34.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin with respect to Ground..-0. Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ............................................... 20.0 ...
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Table 34-1. Current Consumption Symbol Parameter (2) Module current consumption RC32M RC32M w/DFLL RC2M RC2M w/DFLL RC32K PLL Watchdog normal mode BOD Continuous mode BOD Sampled mode Internal 1.00 V ref Temperature reference RTC with int. 32 kHz RC as ...
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Operating Voltage and Frequency Table 34-2. Symbol Clk The maximum CPU clock frequency of the XMEGA A3B devices is depending Figure 34-1 on page 66 Figure 34-1. Maximum Frequency vs. Vcc 8116I–AVR–09/10 Operating voltage and frequency ...
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Flash and EEPROM Memory Characteristics Table 34-3. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 34-4. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the internal 2 MHz oscillator. 2. EEPROM is ...
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ADC Characteristics Table 34-5. ADC Characteristics Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Gain Error Offset Error ADC ADC Clock frequency clk Conversion rate Conversion time (propagation delay) Sampling Time Conversion range AVCC Analog Supply Voltage ...
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DAC Characteristics Table 34-7. DAC Characteristics Symbol Parameter INL Integral Non-Linearity DNL Differential Non-Linearity F Conversion rate clk AREF External reference voltage Reference input impedance Max output voltage Min output voltage Offset factory calibration accuracy Gain factory calibration accuracy ...
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Brownout Detection Characteristics Table 34-10. Brownout Detection Characteristics Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling ...
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POR Characteristics Table 34-12. Power-on Reset Characteristics Symbol Parameter V POR threshold voltage falling Vcc POT- V POR threshold voltage rising Vcc POT+ 34.12 Reset Characteristics Table 34-13. Reset Characteristics Symbol Parameter Minimum reset pulse width Reset threshold voltage ...
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Table 34-18. Maximum load capacitance (CL) and ESR recommendation for 32.768 kHz Crystal Crystal CL [pF] 6.5 9 Table 34-19. Device wake-up time from sleep Symbol Parameter Idle Sleep, Standby and Extended Standby sleep mode Power-save and Power-down Sleep mode ...
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VBAT and Battery Backup Characteristics Table 34-20. VBAT and Battery Backup Characteristics Symbol Parameter Vbat supply voltage range Vbat power-on slope rate Vcc Power-loss slope range main BOD threshold voltage BBBOD required voltage change BBBOD threshold voltage BBBOD detection ...
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Typical Characteristics 35.1 Active Supply Current Figure 35-1. Active Supply Current vs. Frequency Figure 35-2. Active Supply Current vs. Frequency 8116I–AVR–09/ 1.0 MHz External clock 25°C SYS 900 800 700 600 500 400 ...
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Figure 35-3. Active Supply Current vs. Vcc Figure 35-4. Active Supply Current vs. VCC 8116I–AVR–09/ 1.0 MHz External Clock SYS 1000 900 800 700 600 500 400 300 200 100 0 1.6 1.8 2 2.2 2 ...
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Figure 35-5. Active Supply Current vs. Vcc Figure 35-6. Active Supply Current vs. Vcc 8116I–AVR–09/ 2.0 MHz internal RC SYS 2000 1800 1600 1400 1200 1000 800 600 400 200 0 1.6 1.8 2 2.2 2 ...
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Figure 35-7. Active Supply Current vs. Vcc 35.2 Idle Supply Current Figure 35-8. Idle Supply Current vs. Frequency 8116I–AVR–09/ MHz internal RC SYS 2.7 2.8 2 ...
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Figure 35-9. Idle Supply Current vs. Frequency Figure 35-10. Idle Supply Current vs. Vcc 8116I–AVR–09/ MHz 25°C SYS Frequency [MHz] ...
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Figure 35-11. Idle Supply Current vs. Vcc Figure 35-12. Idle Supply Current vs. Vcc 8116I–AVR–09/ 32.768 kHz internal RC SYS 1.6 1.8 2 2.2 2 2.0 MHz ...
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Figure 35-13. Idle Supply Current vs. Vcc Figure 35-14. Idle Supply Current vs. Vcc 8116I–AVR–09/ MHz internal RC prescaled to 8 MHz SYS 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.6 1.8 2 2.2 2.4 f ...
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Power-down Supply Current Figure 35-15. Power-down Supply Current vs. Temperature Figure 35-16. Power-down Supply Current vs. Temperature 8116I–AVR–09/10 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -30 -20 - Temperature [°C] With WDT ...
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Power-save Supply Current Figure 35-17. Power-save Supply Current vs. Temperature 35.5 Pin Pull-up Figure 35-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8116I–AVR–09/10 With WDT, sampled BOD and RTC from ULP enabled 3 2.5 2 1.5 1 0.5 ...
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Figure 35-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage Figure 35-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8116I–AVR–09/ 3.0V CC 160 140 120 100 0 3.3V ...
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Pin Output Voltage vs. Sink/Source Current Figure 35-21. I/O Pin Output Voltage vs. Source Current Figure 35-22. I/O Pin Output Voltage vs. Source Current 8116I–AVR–09/10 Vcc = 1.8V 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ...
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Figure 35-23. I/O Pin Output Voltage vs. Source Current Figure 35-24. I/O Pin Output Voltage vs. Sink Current 8116I–AVR–09/10 Vcc = 3.3V 3.5 3 2.5 2 1.5 1 0.5 0 -20 -18 -16 -14 -12 Vcc = 1.8V 1.8 1.6 ...
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Figure 35-25. I/O Pin Output Voltage vs. Sink Current Figure 35-26. I/O Pin Output Voltage vs. Sink Current 8116I–AVR–09/10 Vcc = 3.0V 0.7 0.6 0.5 0.4 0.3 0.2 0 Vcc = 3.3V 0.7 0.6 ...
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Pin Thresholds and Hysteresis Figure 35-27. I/O Pin Input Threshold Voltage vs. V Figure 35-28. I/O Pin Input Threshold Voltage vs. V 8116I–AVR–09/ I/O Pin Read as “1” IH 2.5 2 1.5 1 0.5 0 1.6 1.8 ...
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Figure 35-29. I/O Pin Input Hysteresis vs. V Figure 35-30. Reset Input Threshold Voltage vs. V 8116I–AVR–09/10 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2 2.2 2 I/O Pin Read as “1” IH 1.8 1.6 ...
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Figure 35-31. Reset Input Threshold Voltage vs. V 35.8 Bod Thresholds Figure 35-32. BOD Thresholds vs. Temperature 8116I–AVR–09/ I/O Pin Read as “0” IL 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 ...
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Figure 35-33. BOD Thresholds vs. Temperature 35.9 Oscillators and Wake-up Time 35.9.1 Internal 32.768 kHz Oscillator Figure 35-34. Internal 32.768 kHz Oscillator Calibration Step Size 8116I–AVR–09/10 BOD Level = 2.9V 3.06 3.04 3.02 3 2.98 2.96 2.94 2.92 2.9 -40 ...
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Internal 2 MHz Oscillator Figure 35-35. Internal 2 MHz Oscillator CALA Calibration Step Size -0.10 % -0.20 % -0.30 % Figure 35-36. Internal 2 MHz Oscillator CALB Calibration Step Size 8116I–AVR–09/10 ° - ...
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Internal 32 MHZ Oscillator Figure 35-37. Internal 32 MHz Oscillator CALA Calibration Step Size Figure 35-38. Internal 32 MHz Oscillator CALB Calibration Step Size 8116I–AVR–09/10 ° - 0.60 % 0.50 ...
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Module current consumption Figure 35-39. AC current consumption vs. Vcc Figure 35-40. Power-up current consumption vs. Vcc 8116I–AVR–09/10 Low-power Mode 120 100 1.6 1.8 2 2.2 2.4 700 600 500 400 300 200 100 ...
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Reset Pulsewidth Figure 35-41. Minimum Reset Pulse Width vs. Vcc 35.12 PDI Speed Figure 35-42. PDI Speed vs. Vcc 8116I–AVR–09/10 120 100 1.6 1.8 2 2.2 2 ...
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... Errata 36.1 ATxmega256A3B 36.1.1 rev. C • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • ADC has increased INL error for some operating conditions • ADC gain stage non-functional • ...
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Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition ...
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Problem fix/Workaround None. 7. Configuration of PGM and CWCM not as described in XMEGA A Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not ...
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DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this ...
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Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 18. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768 kHz crystal ...
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TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 37.1 8116I - 09/10 1. 37.2 8116H - 08/10 ...
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... Characteristics” on page Updated ”Errata” on page 95. Updated ”Ordering Information” on page Editorial updates. Added ”Errata” on page 95 for ATxmega256A3B rev B. Added ”Errata” on page 95 for ATxmega256A3B rev A. XMEGA A3B 72. ”Oscillators and Wake-up Time” on page Figure 35-42 on page 94. 64. 67. 64. 74. 2. 90. ...
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Initial version. XMEGA A3B 103 ...
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Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 4 4 Resources ................................................................................................. 6 5 Disclaimer ................................................................................................. 6 6 AVR CPU ................................................................................................... 7 7 Memories .................................................................................................. ...
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Power Management and Sleep Modes ................................................. 20 12 System Control and Reset .................................................................... 22 13 Battery Backup System ......................................................................... 24 14 PMIC - Programmable Multi-level Interrupt Controller ....................... 26 15 I/O Ports .................................................................................................. 28 16 T/C - 16-bit Timer/Counter ...
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RTC32 - 32-bit Real-Time Counter ........................................................ 36 20 TWI - Two Wire Interface ....................................................................... 37 21 SPI - Serial Peripheral Interface ............................................................ 38 22 USART ..................................................................................................... 39 23 IRCOM - IR Communication Module .................................................... 40 24 Crypto Engine ........................................................................................ ...
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Program and Debug Interfaces ............................................................. 49 30 Pinout and Pin Functions ...................................................................... 50 31 Peripheral Module Address Map .......................................................... 57 32 Instruction Set Summary ...................................................................... 58 33 Packaging information .......................................................................... 62 34 Electrical Characteristics ...................................................................... 64 35 Typical Characteristics ...
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... Thresholds and Hysteresis ..............................................................................87 35.8Bod Thresholds .....................................................................................................89 35.9Oscillators and Wake-up Time ..............................................................................90 35.10Module current consumption ...............................................................................93 35.11Reset Pulsewidth .................................................................................................94 35.12PDI Speed ...........................................................................................................94 36 Errata ....................................................................................................... 95 36.1ATxmega256A3B ..................................................................................................95 37 Datasheet Revision History ................................................................ 101 37.18116I - 09/10 .......................................................................................................101 37.28116H - 08/10 ......................................................................................................101 37.38116G - 05/10 .....................................................................................................101 37.48116F - 09/09 ......................................................................................................102 37.58116E - 06/09 ......................................................................................................102 37.68116D - 04/09 ......................................................................................................102 37 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...