ATXMEGA256A3B-AU Atmel, ATXMEGA256A3B-AU Datasheet - Page 100

• Manufacturer Part Number: ATXMEGA256A3B-AU
• Description: MCU AVR 256KB FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA256A3B-AU

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Controller Family/series: ATXMEGA
• No. Of I/o's: 49
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• Rohs Compliant: Yes
• Processor Series: XMEGA
• Core: AVR
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 49
• Number Of Timers: 7
• Operating Supply Voltage: 2.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8116I–AVR–09/10
21. TWI START condition at bus timeout will cause transaction to be dropped
22. TWI Data Interrupt Flag (DIF) erroneously read as set
23. WDR instruction inside closed window will not issue reset
24. Pending asynchronous RTC32-interrupts will not wake up device
25. XOSCDFD can not be cleared by writing one to bit location
26. Maximum operating frequency below 1.76V is 8 MHz
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a
START is detected, the transaction will be dropped.
Problem fix/Workaround
None.
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock
cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command
will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
When a WDR instruction is execute within one ULP clock cycle after updating the window
control register, the counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.
Asynchronous Interrupts from the 32-bit Real-Time-Counter that is pending when the sleep
instruction is executed, will be ignored until the device is woken from another source or the
source triggers again.
Problem fix/Workaround
None.
The Crystal Oscillator Failure Detection Flag (XOSCFDF) can not be cleared by writing one
to its bit location. The bit can only be cleared by issuing a reset to the VBAT domain.
Problem fix/Workaround
None.
To ensure correct operation, the maximum operating frequency below 1.76V VCC is 8 MHz.
Problem fix/Workaround
None, avoid running the device outside this frequency and voltage limitation.
XMEGA A3B
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