Z8F011AQB020EC Zilog, Z8F011AQB020EC Datasheet - Page 113

• Manufacturer Part Number: Z8F011AQB020EC
• Description: IC ENCORE XP MCU FLASH 1K 8-QFN
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F011AQB020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-VQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: 269-3644

PS022825-0908
Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error
conditions). Follow the steps below to configure the UART receiver for interrupt-driven
operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode
7. Write the device address to the Address Compare Register (automatic MULTIPRO-
8. Write to the UART Control 0 register to:
9. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Checks the UART Status 0 register to determine the source of the interrupt - error,
2. Reads the data from the UART Receive Data register if the interrupt was because of
rate.
alternate function operation.
the acceptable priority.
functions, if appropriate.
–
–
–
CESSOR modes only).
–
–
break, or received data.
data available. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the MULTIPROCESSOR mode bits MPMD[1:0].
Set the Multiprocessor Mode Select (MPEN) to Enable MULTIPROCESSOR
mode.
Set the Multiprocessor Mode Bits, MPMD[1:0], to select the acceptable address
matching scheme.
Configure the UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z8 Encore!
DMA block)
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if appropriate and if multiprocessor mode is not enabled, and select
either even or odd parity.
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP
Product Specification
®
®
devices without a
F082A Series
102