Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 96

• Manufacturer Part Number: Z8F0813HJ005EG
• Description: IC Z8 ENCORE MCU FLASH 8K 28SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0813HJ005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4182; Z8F0813HJ005EG

PS025203-0405
Caution:
PRES—Prescale value.
The timer input clock is divided by 2
caler is reset each time the Timer is disabled. This reset ensures proper clock division each
time the Timer is restarted.
TMODE—Timer mode
This field along with the TMODEHI bit in TxCTL0 register determines the operating
mode of the timer. TMODEHI is the most significant bit of the Timer mode selection
value.
When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, Tx-
OUT will change to whatever state the TPOL bit is in.The timer does not need to be en-
abled for that to happen. Also, the Port data direction sub register is not needed to be set
to output on TxOUT. Changing the TPOL bit with the timer enabled and running does
not immediately change the TxOUT.
number of cycles time delay before the Timer Output and the Timer Output
Complement is forced to High (1).
1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0)
when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon
PWM count match and forced High (1) upon Reload.When enabled, the Timer Output
Complement is forced High (1) upon PWM count match and forced Low (0) upon
Reload. The PWMD field in TxCTL0 register is a programmable delay to control the
number of cycles time delay before the Timer Output and the Timer Output
Complement is forced to Low (0).
CAPTURE RESTART mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARATOR COUNTER mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
0000 = One-Shot mode
0001 = Continuous mode
0010 = Counter mode
P R E L I M I N A R Y
PRES
, where PRES can be set from 0 to 7. The pres-
Z8 Encore!
Product Specification
®
Z8F0823 Series
Timers
79