Z8F3222VS020SG Zilog, Z8F3222VS020SG Datasheet - Page 177

• Manufacturer Part Number: Z8F3222VS020SG
• Description: IC ENCORE MCU FLASH 32K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F3222VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F322x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4263; Z8F3222VS020SG

DMA Control Register Definitions
Table 77. DMAx Control Register (DMAxCTL)
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
Caution:
DMAx Control Register
DEN
7
The DMAx Control register (see
operation for DMAx.
DEN—DMAx Enable
0 = DMAx is disabled and data transfer requests are disregarded.
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the
DLE—DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End
Address data is transferred.
–
–
–
When using the DMA_ADC to perform conversions on multiple ADC inputs,
the Analog-to-Digital Converter must be configured for SINGLE-SHOT mode.
If the ADC_IN field in the DMA_ADC Control Register is greater than 000b,
the ADC must be in SINGLE-SHOT mode.
CONTINUOUS mode operation of the ADC can only be used in conjunction
with DMA_ADC if the ADC_IN field in the DMA_ADC Control Register is re-
set to 000b to enable conversion on ADC Analog Input 0 only.
trigger source.
Enable the DMA_ADC interrupt request, if desired
Select the number of ADC Analog Inputs to convert
Enable the DMA_ADC channel
DLE
6
DDIR
5
IRQEN
Table 77
4
FB0H, FB8H
R/W
0
on page 163) enables and selects the mode of
WSEL
3
Z8 Encore! XP
2
Direct Memory Access Controller
Product Specification
RSS
1
®
F64XX Series
0
163