EZ80F92AZ020SC00TR Zilog, EZ80F92AZ020SC00TR Datasheet - Page 137
![IC ACCLAIM MCU 128KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F92AZ020SC00TR
Manufacturer Part Number
EZ80F92AZ020SC00TR
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F92AZ020SC00T
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Serial Peripheral Interface
PS015313-0508
Note:
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. The SPI is a full-duplex, synchronous, character-oriented
communication channel that employs a four-wire interface. The SPI block consists of a
transmitter, receiver, baud rate generator, and control unit. During an SPI transfer, data is
sent and received simultaneously by both the master and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock. The SPI
may be configured as either a master or a slave. The connection of two SPI devices (one
master and one slave) and the direction of data transfer is displayed in
Figure 30
DATAIN
When using the SPI module in the master mode, Port B2 must not be used as
GPIO. If you do attempt to use it as GPIO, even though it is assigned as a stan-
dard Mode 1 output pin, outputting a logic low on the pin will cause the SPI to
trigger a Mode Fault.
on page 131.
SS
MISO
Bit 0
Baud Rate
Generator
8-Bit Shift Register
MASTER
Figure 29.SPI Master Device
Bit 7
SCK
DATAOUT
CLKOUT
Product Specification
Serial Peripheral Interface
eZ80F92/eZ80F93
Figure 29
and
130
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