M38039G6HKP#U0 Renesas Electronics America, M38039G6HKP#U0 Datasheet - Page 67

• Manufacturer Part Number: M38039G6HKP#U0
• Description: IC 740/3803 MCU QZROM 64LQFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039G6HKP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H QzROM version)
REJ03B0166-0113 Rev.1.13
Page 65 of 100
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example,
because of a software run-away). The watchdog timer consists of
an 8-bit watchdog timer L and an 8-bit watchdog timer H.
• Watchdog Timer Initial Value
Watchdog timer L is set to “FF
“FF
001E
signal can be used, such as the STA, LDM, CLB, etc. Data can
only be written to bits 6 and 7 of the watchdog timer control
register. Regardless of the value written to bits 0 to 5, the above-
mentioned value will be set to each timer.
Bit 6 can be written only once after releasing reset. After
rewriting it is disable to write any data to this bit.
• Watchdog Timer Operations
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register (address 001E
An internal reset occurs at an underflow of the watchdog timer
H. The reset is released after waiting for a reset release time and
the program is processed from the reset vector address.
Accordingly, programming is usually performed so that writing
to the watchdog timer control register may be started before an
underflow. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
Fig 59. Block diagram of Watchdog timer
Fig 60. Structure of Watchdog timer control register
16
16
” by writing to the watchdog timer control register (address
) or at a reset. Any write instruction that causes a write
Main clock division
ratio selection bits (Note)
X
X
CIN
IN
b7
RESET
STP instruction function selection bit
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
16
“10”
“00”
“01”
” and watchdog timer H is set to
STP instruction
1/16
“FF
watchdog timer
control register is
written to.
Aug 21, 2009
16
” is set when
Watchdog timer L (8)
b0
Watchdog timer control register
(WDTCON : address 001E
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function selection bit
Watchdog timer H count source selection bit
16
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
0: Watchdog timer L underflow
1: f(X
).
IN
• Bit 6 of Watchdog Timer Control Register
• When bit 6 of the watchdog timer control register is “0”, the
• When bit 6 is “1”, execution of STP instruction causes an
The following shows the period between the write execution to
the watchdog timer control register and the underflow of
watchdog timer H.
Bit 7 of the watchdog timer control register is “0”:
Bit 7 of the watchdog timer control register is “1”:
Note. The watchdog timer continues to count even while waiting for a
)/16 or f(X
MCU enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting
watchdog timer does not stop.
internal reset. When this bit is set to “1” once, it cannot be
rewritten to “0” by program. Bit 6 is “0” at reset.
“0”
“1”
Watchdog timer H count
source selection bit
stop release. Therefore, make sure that watchdog timer H does not
underflow during this period.
when X
when X
when X
when X
(Note.)
CIN
CIN
IN
CIN
IN
)/16
Watchdog timer H (8)
= 16 MHz; 65.536 ms
= 16 MHz; 256 µs
. When executing the WIT instruction, the
= 32.768 kHz; 32 s
= 32.768 kHz; 125 ms
16
Reset
circuit
)
Data bus
Internal reset
“FF
watchdog timer
control register is
written to.
16
” is set when