R5F21292SNSP#U0 Renesas Electronics America, R5F21292SNSP#U0 Datasheet - Page 275

• Manufacturer Part Number: R5F21292SNSP#U0
• Description: MCU 3/5V 16K+2K 20PIN-SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/29r

Specifications of R5F21292SNSP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/28 Group, R8C/29 Group
Rev.2.10
REJ09B0279-0210
Figure 16.6
SS Status Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
6.
7. When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to
Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits invalid. To set any of these bits to 0, first read 1 then w rite 0.
When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set
to 1 if “L” is applied to the SCS
When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the
SSCRH register is set to 0 (operates as slave device) and the SCS
transfer, the CE bit is set to 1.
Indicates w hen overrun errors occur and receive completes by error reception. If the next serial data receive
operation is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the
ORER bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1.
The RDRF bit is set to 0 w hen reading out the data from the SSRDR register.
Bits TEND and TDRE are set to 0 w hen w riting data to the SSTDR register.
The TDRE bit is set to 1 w hen the TE bit in the SSER register is set to 1 (transmit enabled).
access it.
Sep 26, 2008
b3 b2 b1
SSSR Register
b0
(7)
Bit Symbol
(b4-b3)
Symbol
SSSR
ORER
RDRF
TEND
TDRE
(b1)
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CE
—
—
_____
Conflict error flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Overrun error flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Receive data register full
(1,4)
Transmit end
Transmit data empty
pin input. Refer to 16.2.7 SCS
Address
Bit Name
00BCh
(1, 5)
(1)
(1)
(1, 5, 6)
_____
0 : No conflict errors generated
1 : Conflict errors generated
0 : No overrun errors generated
1 : Overrun errors generated
0 : No data in SSRDR register
1 : Data in SSRDR register
0 : The TDRE bit is set to 0 w hen transmitting
1 : The TDRE bit is set to 1 w hen transmitting
0 : Data is not transferred from registers SSTDR to
1 : Data is transferred from registers SSTDR to
Pin Control and Arbitration for more information.
the last bit of transmit data
the last bit of transmit data
SSTRSR
SSTRSR
_____
pin input changes the level from “L” to “H” during
16. Clock Synchronous Serial Interface
After Reset
Function
00h
(2)
(3)
RW
RW
RW
RW
RW
RW
—
—