HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 41

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2.2.2
Memory data formats are classified into bytes, words, and long words. Byte data can be accessed
from any address, but an address error will occur if you try to access word data starting from an
address other than 2n or long word data starting from an address other than 4n. In such cases, the
data accessed cannot be guaranteed. The hardware stack area, which is referred to by the hardware
stack pointer (SP, R15), uses only long word data starting from address 4n because this area stores
the program counter and status register (figure 2.5).
2.2.3
Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the
MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as long word
data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
is handled as long word data. Consequently, AND instructions with immediate data always clear
the upper 24 bits of the destination register.
Word or long word immediate data is not located in the instruction code but rather is stored in a
memory table. The memory table is accessed by a immediate data transfer instruction (MOV)
using the PC relative addressing mode with displacement.
18 RENESAS
Data Format in Memory
Immediate Data Format
Address 2n
Address 4n
31
Figure 2.4 Data Format in Registers
Figure 2.5 Data Format in Memory
Address m
31
7
15
31
Byte
Word
0
Address m + 1
Long word
23
7
Byte
Long word
0
0
Address m + 2
15
7
15
Byte
Word
0
Address m + 3
7
7
0
Byte
0
0
0
0