HD64F2633RTE28 Renesas Electronics America, HD64F2633RTE28 Datasheet - Page 331

IC H8S MCU FLASH 256K 120-TQFP

HD64F2633RTE28

Manufacturer Part Number
HD64F2633RTE28
Description
IC H8S MCU FLASH 256K 120-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of HD64F2633RTE28

Core Processor
H8S/2600
Core Size
16-Bit
Speed
28MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
73
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
3.5
Bus-Released State
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts except for internal operations.
Bus masters other than the CPU may include the direct memory access controller (DMAC) and
data transfer controller (DTC).
For further details, refer to the relevant microcontroller hardware manual.
3.6
Power-Down State
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode,
software standby mode, and hardware standby mode. There are also two other power-down
modes: medium-speed mode and module stop mode. In medium-speed mode the CPU and other
bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. For details, refer to the relevant microcontroller
hardware manual.
3.6.1
Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bit (SSBY) in the system control register (SYSCR) is cleared to 0. In sleep mode, CPU
operations stop immediately after execution of the SLEEP instruction. The contents of CPU
registers are retained.
3.6.2
Software Standby Mode
A transition to software standby mode is made if the SLEEP instruction is executed while the
SSBY bit in SYSCR is set to 1. In software standby mode, the CPU and clock halt and all on-chip
operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is
supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain
in their existing states.
Section 3 Processing States
Rev. 4.00 Feb 24, 2006 page 315 of 322
REJ09B0139-0400

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