DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 16

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
12.2.1 Timer
Counter (TCNT)
12.5.7 Notes on
Initializing TCNT by
Using the TME Bit
13.3.7 Serial Status
Register (SSR)
13.3.7 Serial Status
Register (SSR)
Rev. 5.00 Sep. 01, 2009 Page xiv of l
REJ09B0071-0500
Page
291
302
320
321
Revision (See Manual for Details)
Description added
TCNT is an 8-bit readable/writable up-counter. TCNT is
initialized to H'00 when the TME bit in TCSR is cleared to 0.
To initialize TCNT to H’00 while the timer is operating, write H’00
to TCNT directly. See 12.5.7, Notes on Initializing TCNT by
Using the TME Bit.
12.5.7 added
Table amended
Table amended
Bit
2
Bit
7
6
Bit Name
TEND
Bit Name
TDRE
RDRF
Initial
Value
1
Initial
Value
1
0
R/W
R
R/W
R/(W) *
R/(W) *
1
1
Description
Transmit End
Indicates that transmission has been ended.
[Setting conditions]
[Clearing conditions]
Description
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
[Clearing conditions]
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive data is
transferred from RSR to RDR
[Clearing conditions]
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF
flag is still set to 1, an overrun error will occur and the
receive data will be lost.
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC *
•
•
•
•
•
•
1-byte serial transmit character
request and transfer transmission data to TDR
(H8S/2268 Group only)
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data
can be written to TDR
When 0 is written to TDRE after reading TDRE = 1
When the DTC *
request and writes data to TDR (H8S/2268 Group
only)
When 0 is written to RDRF after reading RDRF = 1
When the DTC *
transferred data from RDR (H8S/2268 Group only)
2
2
2
is activated by a TXI interrupt
is activated by a TXI interrupt
is activated by an RXI interrupt and