DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 481

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5
IICI is the interrupt source of IIC. Table 14.6 shows each interrupt source and its priority. The
ICCR interrupt enable bit sets each interrupt and the setting is independently sent to the interrupt
controller.
Table 14.6 IIC Interrupt Source
Channel
0
1
14.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 14.7 shows the timing of SCL and SDA output in synchronization with the internal
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output consecutive start and stop conditions, after
issuing the instruction that generates the start condition, read the relevant ports, check that
SCL and SDA are both low, then issue the instruction that generates the stop condition. Note
that SCL may not yet have gone low when BBSY is cleared to 0.
conditions when reading or writing to ICDR.
⎯ Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
⎯ Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
ICDRT to ICDRS)
ICDRS to ICDRR)
Interrupt Source
Usage Notes
Name
IICI0
IICI1
Section 14 I
Enable Bit
IEIC
IEIC
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
Interrupt Source
I
request
I
request
2
2
C bus interface interrupt
C bus interface interrupt
Rev. 5.00 Sep. 01, 2009 Page 429 of 656
Interrupt
Flag
IRIC
IRIC
REJ09B0071-0500
2
C bus, neither
Interrupt
Priority
High
Low