DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 617

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

22.5.3
Figure 22.4 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,
waiting for the oscillation settling time, then changing the RES pin from low to high.
22.6
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the A/D converter are retained.
After reset clearance, all modules other than DTC * are in module stop mode.
When an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
Since the operations of the bus controller and I/O port are stopped when sleep mode is entered at
the all-module stop state (MSTPCR=H'FFFFFFFF), power consumption can further be reduced.
Note: * Supported only by the H8S/2268 Group.
Hardware Standby Mode Timing
Module Stop Mode
Oscillator
RES
STBY
Figure 22.4 Hardware Standby Mode Timing
Rev. 5.00 Sep. 01, 2009 Page 565 of 656
Oscillation
settling
time t
Section 22 Power-Down Modes
osc1
exception
handling
Reset
REJ09B0071-0500