HD6417708RF100A Renesas Electronics America, HD6417708RF100A Datasheet - Page 15

• Manufacturer Part Number: HD6417708RF100A
• Description: IC SUPERH MPU ROMLESS 144LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417708RF100A

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SCI, SmartCard
• Peripherals: POR, WDT
• Number Of I /o: 8
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 3.15 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 On-Chip Oscillation Circuits
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10 Using the WDT.................................................................................................................. 181
9.11 Notes on Board Design...................................................................................................... 184
Section 10 Bus State Controller (BSC)
10.1 Overview............................................................................................................................ 187
8.7.1
8.7.2
8.7.3
Overview............................................................................................................................ 157
9.1.1
Overview of the CPG ........................................................................................................ 158
9.2.1
9.2.2
9.2.3
Clock Operating Modes..................................................................................................... 162
Register Descriptions......................................................................................................... 170
9.4.1
Changing the Frequency.................................................................................................... 174
9.5.1
9.5.2
PLL Standby Function....................................................................................................... 175
9.6.1
9.6.2
Controlling Clock Output .................................................................................................. 176
9.7.1
9.7.2
Overview of the Watchdog Timer (WDT) ........................................................................ 177
9.8.1
9.8.2
WDT Registers .................................................................................................................. 178
9.9.1
9.9.2
9.9.3
9.10.1 Canceling Standbys .............................................................................................. 181
9.10.2 Changing the Frequency....................................................................................... 181
9.10.3 Using Watchdog Timer Mode.............................................................................. 182
9.10.4 Using Interval Timer Mode.................................................................................. 182
9.10.5 Usage Notes.......................................................................................................... 183
10.1.1 Features ................................................................................................................ 187
10.1.2 Block Diagram...................................................................................................... 188
10.1.3 Pin Configuration ................................................................................................. 190
Transition to Hardware Standby Mode ................................................................ 153
Canceling Hardware Standby Mode .................................................................... 154
Hardware Standby Mode Timing ......................................................................... 154
Features ................................................................................................................ 157
CPG Block Diagram............................................................................................. 158
CPG Pin Configuration ........................................................................................ 161
CPG Register Configuration ................................................................................ 161
Frequency Control Register (FRQCR)................................................................. 170
Changing the Multiplication Rate ........................................................................ 174
Changing the Division Ratio ................................................................................ 174
Overview of the PLL Standby Function .............................................................. 175
Usage .................................................................................................................... 175
Clock Modes 0–2.................................................................................................. 176
Clock Modes 3 and 4............................................................................................ 176
Block Diagram of the WDT ................................................................................. 177
Register Configurations........................................................................................ 177
Watchdog Timer Counter (WTCNT) ................................................................... 178
Watchdog Timer Control/Status Register (WTCSR) ........................................... 178
Notes on Register Access ..................................................................................... 180
......................................................................... 157
......................................................................... 187
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