UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 95

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited.
Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00
Falling edge
Rising edge
No capture operation
Falling edge
Rising edge
Both rising and falling edges
When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the
TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 6-
2).
CR000 Capture Trigger
CR000 Capture Trigger
2. ES010, ES000:
2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00
3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR000 set in compare mode even if a
5. When P21 is used as the input pin for the valid edge of TI010, it cannot be used as a timer
6. If the register read period and the input of the capture trigger conflict when CR000 is
7. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5
Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
ES110, ES100:
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
and CR000.
register is used as an external event counter. However, in the free-running mode and in
the clear & start mode using the valid edge of TI000, if CR000 is set to 0000H, an interrupt
request (INTTM000) is generated when CR000 changes from 0000H to 0001H following
overflow (FFFFH).
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR000 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR000 is changed.
capture trigger is input.
output (TO00). Moreover, when P21 is used as TO00, it cannot be used as the input pin
for the valid edge of TI010.
used as a capture register, the read data is undefined (the capture data itself is a normal
value). Also, if the count stop of the timer and the input of the capture trigger conflict,
the capture trigger is undefined.
Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register
during timer operation.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ( PD78F920x ONLY)
This means a 1-pulse count operation cannot be performed when this
Bits 5 and 4 of prescaler mode register 00 (PRM00)
Bits 7 and 6 of prescaler mode register 00 (PRM00)
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
User’s Manual U18172EJ3V0UD
TI000 Pin Valid Edge
TI010 Pin Valid Edge
ES010
ES110
0
0
1
0
0
1
ES000
ES100
1
0
1
0
1
1
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