UPD78F1152AGK-GAK-AX Renesas Electronics America, UPD78F1152AGK-GAK-AX Datasheet - Page 871

• Manufacturer Part Number: UPD78F1152AGK-GAK-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGK-GAK-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Standby
function
Reset
function
Function
OSTS:
Oscillation
stabilization time
select register
STOP mode
Details of
Function
−
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
Setting the oscillation stabilization time to 20
Before changing the setting of the OSTS register, confirm that the count operation of
the OSTC register is completed.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
To stop the internal low-speed oscillation clock in the STOP mode, use an option
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0
(WDSTBYON) of 000C0H = 0), and then execute the STOP instruction.
To shorten oscillation stabilization time after the STOP mode is released when the
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the execution of the
STOP instruction. Before changing the CPU clock from the internal high-speed
oscillation clock to the high-speed system clock (X1 oscillation) after the STOP mode
is released, check the oscillation stabilization time with the oscillation stabilization
time counter status register (OSTC).
For an external reset, input a low level for 10
(If an external reset is effected upon power application, the period during which the
supply voltage is outside the operating range (V
μ
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and
internal low-speed oscillation clock stop oscillating. External main system clock input
becomes invalid.
When the STOP mode is released by a reset, the RAM contents in the STOP mode
are held during reset input. However, because SFR and 2nd SFR are initialized, the
port pins become high-impedance, except for P130, which is set to low-level output.
s. However, the low-level input may be continued before POC is released.)
OSTS
APPENDIX B LIST OF CAUTIONS
User’s Manual U17893EJ8V0UD
Cautions
μ
μ
s or less is prohibited.
s or more to the RESET pin.
DD
< 1.8 V) is not counted in the 10
p.623
p.623
p.623
p.623
p.623
p.623
p.629
p.631
p.631
p.631
p.636
p.636
p.636
(24/34)
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