UPD78F1152AGK-GAK-AX Renesas Electronics America, UPD78F1152AGK-GAK-AX Datasheet - Page 901

• Manufacturer Part Number: UPD78F1152AGK-GAK-AX
• Description: MCU 16BIT 78K0R/KX3 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1152AGK-GAK-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5th edition
7th edition
Edition
Change of A.4.1 When using flash memory programmer FG-FP4 and FL-PR4
Change of A.4.2 When using on-chip debug emulator with programming
function QB-MINI2
Change of A.5.2 When using on-chip debug emulator with programming
function QB-MINI2
Addition of expanded-specification products,
78F1155A, 78F1156A
Addition of (A) grade products of expanded-specification products,
μ
Change of related documents
Addition of 1.1 Differences Between Conventional-Specification Products
(
Addition of Cautions 4 to 1.5 Pin Configuration (Top View)
Modification of 1.7 Block Diagram
Change of description in 2.2.14 AV
Change of description in 2.2.15 AV
Change of description in 2.2.17 RESET
Change of descriptions of AV
of Unused Pins
Addition of Note to Figures 3-1 to 3-5
Change of figure in Remark of 3.1 Memory Space
Change of description in 3.1.1 (1) Vector table area
Change of description in 3.1.2 Mirror area
Change of description and addition and change of Caution in 3.1.3 Internal data
memory space
Addition of Cautions to 3.2.1 (3) Stack pointer (SP)
Modification of Table 3-5 SFR List
Addition of Cautions 4 to Figure 4-41 Format of A/D Port Configuration Register
(ADPC)
Change of Cautions 3 and 5 in Figure 5-8 Format of Operation Speed Mode
Control Register (OSMC)
Change of Figure 5-13 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Change of Figure 5-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0)) and description of <1>
Change of 5.6.3 (1) <1> Setting P123/XT1 and P124/XT2 pins (CMC register)
Addition of description to 5.6.3 (3) Example of setting procedure when stopping
the subsystem clock
Change of and deletion of Note in Figure 5-15 CPU Clock Status Transition
Diagram
Addition of Note in Table 5-5. Changing CPU Clock
Change of Table 5-6 Maximum Time Required for Main System Clock
Switchover
μ
PD78F1152A(A), 78F1153A(A), 78F1154A(A), 78F1155A(A), 78F1156A(A)
PD78F115x) and Expanded-Specification Products (
REF0
APPENDIX C REVISION HISTORY
, AV
User’s Manual U17893EJ8V0UD
REF0
REF1
Description
REF1
, and RESET pin in Table 2-4 Connection
μ
PD78F1152A, 78F1153A, 78F1154A,
μ
PD78F115xA)
APPENDIX A
DEVELOPMENT
TOOLS
INTRODUCTION
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
Chapter
−
(15/20)
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